MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 57
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MAX9263GCB/V+T
Manufacturer Part Number
MAX9263GCB/V+T
Description
Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
Manufacturer
Maxim Integrated
Datasheet
1.MAX9263GCBVT.pdf
(71 pages)
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Four capacitors—two
at the serializer output and two at the deserializer input—
are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
voltage. AC-coupling blocks low-frequency ground shifts
and low-frequency common-mode noise.
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the CML receiver termination
resistor (R
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(R
transmission line impedance (usually 100I). This leaves
the capacitor selection to change the system time con-
stant. Use at least 0.2FF high-frequency surface-mount
ceramic capacitors, with sufficient voltage rating to with-
stand a short to battery, to pass the lower speed reverse
control-channel signal. Use capacitors with a case size
less than 3.2mm x 1.6mm to have lower parasitic effects
to the high-speed signal.
The serializer uses an AVDD and DVDD of 1.7V to 1.9V,
while the deserializer uses an AVDD and DVDD of 3.0V
to 3.6V. All single-ended inputs and outputs on the
serializer/deserializer derive power from an IOVDD of
1.7V to 3.6V, which scale with IOVDD. Proper voltage-
supply bypassing is essential for high-frequency circuit
stability.
Interconnect for CML typically has a differential imped-
ance of 100I. Use cables and connectors that have
Table 21. Suggested Connectors and
Cables for GMSL
TD
Rosenberger
VENDOR
+ R
Nissei
JAE
Power-Supply Circuits and Bypassing
TR
Selection of AC-Coupling Capacitors
TR
))/4. R
), the CML driver termination resistor (R
TD
D4S10A-40ML5-Z
and R
CONNECTOR
GT11L-2S
MX38-FF
Cables and Connectors
TR
are required to match the
HDCP Gigabit Multimedia Serial
F-2WME AWG28
AC-Coupling
A-BW-Lxxxxx
Dacar 538
CABLE
Link Serializer/Deserializer
TD
),
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables tend to generate less EMI due to magnetic-field
canceling effects. Balanced cables pick up noise as
common-mode rejected by the CML receiver. Table 21
lists the suggested cables and connectors used in the
GMSL link.
Separate the digital signals and CML high-speed sig-
nals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML, and digital sig-
nals. Layout PCB traces close to each other for a 100I
differential characteristic impedance. The trace dimen-
sions depend on the type of trace used (microstrip
or stripline). Note that two 50I PCB traces do not
have 100I differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
Route the PCB traces for a CML channel (there are two
conductors per CML channel) in parallel to maintain the
differential characteristic impedance. Avoid vias. Keep
PCB traces that make up a differential pair equal length
to avoid skew within the differential pair.
The serializer/deserializer ESD tolerance is rated for
Human Body Model, IEC 61000-4-2, and ISO 10605. The
ISO 10605 and IEC 61000-4-2 standards specify ESD
tolerance for electronic systems. The serial link I/O are
tested for ISO 10605 ESD protection and IEC 61000-4-2
ESD protection. All pins are tested for the Human Body
Model. The Human Body Model discharge components
are C
61000-4-2 discharge components are C
R
ponents are C
Figure 35. Human Body Model ESD Test Circuit
D
= 330I (Figure 36). The ISO 10605 discharge com-
S
VOLTAGE
SOURCE
= 100pF and R
HIGH-
DC
CHARGE-CURRENT-
S
LIMIT RESISTOR
= 330pF and R
1MI
100pF
C
S
D
= 1.5kI (Figure 35). The IEC
RESISTANCE
DISCHARGE
STORAGE
CAPACITOR
1.5kI
R
D
D
= 2kI (Figure 37).
ESD Protection
Board Layout
S
= 150pF and
DEVICE
UNDER
TEST
57