MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 33

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

The parallel input/outputs have two selectable modes,
24-bit mode and 32-bit mode. In 24-bit mode, DIN[28:21]
are not available. For both modes, the SD, SCK, and WS
pins are for I
pixel clock rates from 8.33MHz to 104MHz for 24-bit
mode and 6.25MHz to 78MHz for 32-bit mode.
Table 3 lists the HDCP bit mapping for the parallel inputs.
DIN18/HS and DIN19/VS are reserved for HSYNC and
VSYNC, respectively. The serializer/deserializer have
HDCP encryption on DIN[17:0] and the I
mode has additional HDCP encryption on DIN[26:21].
DIN[28:27] and DIN20 do not have HDCP encryption. SD,
when used as an additional data input (AUDIOEN = 0),
also does not have HDCP encryption.
Table 3. HDCP Mapping and Bus Width Selection
*Bit assignments of DIN[28:0] are interchangeable if HDCP is not used.
**HDCP encryption on SD when used as an I
Figure 22. 24-Bit Mode Serial Link Data Format
HDCP Bitmapping and Bus-Width Selection
INPUT BITS
DIN[26:21]
DIN[28:27]
DIN18/HS
DIN[17:0]
DIN19/VS
DIN20
SD
2
S audio. The serializer/deserializer use
HDCP MAPPING*
Not Available
Not Available
NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE
DIN0
R0
RGB
HS
DE
SD
VS
24-BIT MODE (BWS = LOW)
ACCORDINGLY ON BOTH SIDES OF THE LINK.
ONLY DIN[17:0], AND ACB HAVE HDCP ENCRYPTION.
DIN1
R1
HDCP Gigabit Multimedia Serial
RGB DATA
2
2
S signal.
S input. 32-bit
HDCP ENCRYPTION
DIN17
Link Serializer/Deserializer
B5
CAPABILITY
24 BITS
I
DIN18 DIN19 DIN20
Yes
2
No
No
No
HS
—
—
S**
CONTROL BITS
The serializer uses CML signaling with programmable
pre/deemphasis and AC-coupling. The deserializer uses
AC-coupling and programmable channel equalization.
Together, the GMSL link can operate at full speed over
STP cable lengths to 15m or more.
The serializer scrambles and encodes the input data and
sends the 8b/10b coded signal through the serial link.
The deserializer recovers the embedded serial clock and
then samples, decodes, and descrambles before out-
putting the data. Figures 22 and 23 show the serial-data
packet format after unscrambling and 8b/10b decoding.
In 24-bit or 32-bit mode, 21 or 29 bits map to the paral-
lel outputs. The audio channel bit (ACB) contains an
encoded audio signal derived from the three I
(SD, SCK, and WS). The forward control channel (FCC)
VS
DE
Serial Link Signaling and Data Format
CHANNEL
AUDIO
ACB
BIT
HDCP MAPPING*
CHANNEL BIT
CONTROL-
FORWARD
FCC
CNTL
RGB
RGB
HS
DE
SD
VS
32-BIT MODE (BWS = HIGH)
CHECK BIT
PACKET
PARITY
PCB
HDCP ENCRYPTION
CAPABILITY
I
Yes
Yes
2
No
No
No
No
S**
2
S signals
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