C8051F566-IMR Silicon Labs, C8051F566-IMR Datasheet - Page 225

• Manufacturer Part Number: C8051F566-IMR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F566-IMR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

Table 22.3. Sources for Hardware Changes to SMB0CN
Bit
MASTER
TXMODE
STA
STO
ACKRQ
ARBLOST
ACK
SI
Set by Hardware When:

















A START is generated.
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed.
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low 
(ACKNOWLEDGE).
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Rev. 1.1
C8051F55x/56x/57x
Cleared by Hardware When:











A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
Must be cleared by software.
A pending STOP is generated.
After each ACK cycle.
Each time SI is cleared.
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.
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