C8051F567-IQR Silicon Labs, C8051F567-IQR Datasheet - Page 137

• Manufacturer Part Number: C8051F567-IQR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 2 kB SPI UART I2C
• Manufacturer: Silicon Labs

Specifications of C8051F567-IQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

16.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
16.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 16.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
monitor must be enabled to the higher setting (VDMLVL = 1) and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the V
set to the high level, any erase or write performed on Flash memory will cause a Flash Error device
reset.
RST
DD
. A delay occurs before the device is released from reset; the delay decreases as the V
monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V
DD
Logic HIGH
Logic LOW
DD
ramp time is defined as how fast V
2.45
2.25
2.0
1.0
RST
monitor reset timing.
, the CIP-51 will be released from the reset state. Note that even though internal data
Figure 16.2. Power-On and V
/RST
V
RST
DD
DD
Monitor
Power-On
monitor is disabled by code and a software reset is performed, the
Reset
T
PORDelay
Rev. 1.1
DD
DD
ramps from 0 V to V
Monitor Reset Timing
DD
C8051F55x/56x/57x
to drop below V
Monitor
Reset
VDD
DD
DD
monitor is enabled following a
monitor is not enabled and
RST
). Figure 16.2. plots the
RST
VDD
, the power supply
DD
DD
dropped below
t
settles above
DD
DD
ramp time
returns
137
DD
DD