C8051F305-GSR Silicon Labs, C8051F305-GSR Datasheet - Page 87

• Manufacturer Part Number: C8051F305-GSR
• Description: 8-bit Microcontrollers - MCU 2KB 14Pin MCU
• Manufacturer: Silicon Labs

Specifications of C8051F305-GSR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

(Note: Do not use read-modify-write operations (ORL, ANL) on this register)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
—
R
UNUSED. Read = 0. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
Write
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active-low).
Read
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
SWRSF: Software Reset Force and Flag.
Write
0: No Effect.
1: Forces a system reset.
Read
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
Write:
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
Read:
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or
a V
lowing the reset. Writing this bit enables/disables the V
Write:
0: V
1: V
Read:
0: Last reset was not a power-on or V
1: Last reset was a power-on or V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
FERROR C0RSEF
DD
DD
DD
Bit6
R
monitor reset. In either case, data memory should be considered indeterminate fol-
monitor disabled.
monitor enabled.
SFR Definition 9.1.
R/W
Bit5
SWRSF WDTRSF MCDRSF
R/W
Bit4
DD
Rev. 2.9
monitor reset; all other reset flags indeterminate.
DD
RSTSRC: Reset Source
Bit3
R
monitor reset.
R/W
Bit2
C8051F300/1/2/3/4/5
DD
monitor.
PORSF
R/W
Bit1
PINRSF
Bit0
R
SFR Address:
Reset Value
Variable
0xEF
87