C8051F343-GMR Silicon Labs, C8051F343-GMR Datasheet - Page 41
![no-image](/images/no-image-200.jpg)
C8051F343-GMR
Manufacturer Part Number
C8051F343-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 32KB 10 ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F349-GMR.pdf
(276 pages)
Specifications of C8051F343-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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5.
The ADC0 subsystem for the C8051F34x devices consists of two analog multiplexers (referred to collec-
tively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window
detector are all configured under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages
at port pins, the Temperature Sensor output, or V
tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-
system is in low power shutdown when this bit is logic 0.
* 21 Selections on 32-pin package
Port I/O
Port I/O
20 Selections on 48-pin package
Sensor
VREF
Pins*
Pins*
Temp
GND
VDD
10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
Negative
Positive
(AIN+)
AMUX
AMUX
(AIN-)
Input
Input
Figure 5.1. ADC0 Functional Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
AMX0P
AMX0N
DD
Rev. 1.3
with respect to a port pin, VREF, or GND. The connec-
AIN+
AIN-
ADC0CF
ADC
10-Bit
VDD
SAR
ADC0GTH ADC0GTL
ADC0LTH
ADC0CN
ADC0LTL
Conversion
Start
100
000
001
010
011
101
32
AD0WINT
Compare
Window
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
Logic
41
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