74LVC125ABQ-G NXP Semiconductors, 74LVC125ABQ-G Datasheet

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74LVC125ABQ-G

Manufacturer Part Number
74LVC125ABQ-G
Description
Buffers & Line Drivers QUAD BUFFR/LINE DRVR
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC125ABQ-G

Product Category
Buffers & Line Drivers
Rohs
yes
Number Of Input Lines
8
Number Of Output Lines
4
Polarity
Non-Inverting
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-762-14
High Level Output Current
- 24 mA
Logic Family
LVC
Logic Type
CMOS
Low Level Output Current
24 mA
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
4
Output Type
3-State
Propagation Delay Time
2.4 ns
Factory Pack Quantity
3000
Part # Aliases
74LVC125ABQ,115
1. General description
2. Features and benefits
The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs
(nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs.
74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 6 — 5 March 2013
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 2.3 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
ESD protection:
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Product data sheet

Related parts for 74LVC125ABQ-G

74LVC125ABQ-G Summary of contents

Page 1

... Quad buffer/line driver with 5 V tolerant input/outputs; 3-state Rev. 6 — 5 March 2013 1. General description The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3 devices. When disabled 5.5 V can be applied to the outputs ...

Page 2

... Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C SO14 74LVC125AD 40 C to +125 C SSOP14 74LVC125ADB 74LVC125APW 40 C to +125 C TSSOP14 74LVC125ABQ 40 C to +125 C DHVQFN14 4. Functional diagram 1OE ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 1OE 125 4 2OE GND 7 001aad045 Fig 4. Pin configuration for SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 1A, 2A, 3A 1Y, 2Y, 3Y ...

Page 4

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage 2.7 V ...

Page 6

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t propagation delay pd t enable time en t disable time dis t output skew time sk(o) C power dissipation PD capacitance [1] Typical values are measured the same as t and t ...

Page 7

... NXP Semiconductors 11. AC waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 6. The input nA to output nY propagation delays nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH ...

Page 8

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 9 ...

Page 9

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 10 ...

Page 11

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1 ...

Page 13

... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge MM Machine Model HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date 74LVC125A v.6 20130305 • Modifications: Features list corrected (errata) 74LVC125A v ...

Page 14

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... Quad buffer/line driver with 5 V tolerant input/outputs; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations ...

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