72V3640L15PF IDT, 72V3640L15PF Datasheet - Page 27

• Manufacturer Part Number: 72V3640L15PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3640L15PF

• Part # Aliases: IDT72V3640L15PF

NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
Q
Q0 - Qn
D
D0 - Dn
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
WCLK
WCLK
0
0
RCLK
RCLK
of WCLK and the rising edge of RCLK is less than t
the rising edge of the RCLK and the rising edge of the WCLK is less than t
WEN
SKEW1
WEN
SKEW1
REN
- D
- Q
REN
FF
EF
OE
n
n
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
SKEW1
t
SKEW1
OLZ
t
ENH
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
REF
t
A
(1)
t
OE
+ 1*T
t
RCLK
ENH
t
SKEW1
t
ENS
t
A
t
DS
+ t
1
D
(1)
REF.
NO WRITE
0
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
t
SKEW1
t
DH
ENH
LAST WORD
, then EF deassertion may be delayed one extra RCLK cycle.
1
2
t
WFF
t
DS
t
OHZ
t
t
t
CLKH
DS
ENS
SKEW1
D
D
1
X
NO OPERATION
t
, then the FF deassertion may be delayed one extra WCLK cycle.
WFF
TM
DATA READ
27
t
t
ENH
DH
t
36-BIT FIFO
t
DH
CLK
2
t
CLKL
t
t
CLKH
ENS
t
REF
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
t
ENS
ENH
LAST WORD
t
A
1
NO WRITE
COMMERCIAL AND INDUSTRIAL
t
ENH
t
A
REF
2
TEMPERATURE RANGES
). If the time between the rising edge
WFF
NEXT DATA READ
t
t
ENS
WFF
OCTOBER 22, 2008
t
). If the time between
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
4667 drw12
t
DH
t
4667 drw13
WFF
D
1