72V3640L15PF IDT, 72V3640L15PF Datasheet - Page 32

• Manufacturer Part Number: 72V3640L15PF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V3640L15PF

• Part # Aliases: IDT72V3640L15PF

NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Q
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
WCLK
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680 and 32,768 for the IDT72V3690.
0
RCLK
WEN
1
REN
- Q
PAE
PAF
= first word written to the FIFO after Master Reset, W
HF
EF
RT
n
t
ENS
W
x
t
A
t
ENS
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
W
t
RTS
x+1
2
= second word written to the FIFO after Master Reset.
1
t
A
t
t
ENH
HF
t
SKEW2
1
W
1 (3)
TM
32
36-BIT FIFO
2
t
PAFS
2
t
A
W
2 (3)
3
COMMERCIAL AND INDUSTRIAL
t
t
PAES
A
TEMPERATURE RANGES
W
3 (3)
OCTOBER 22, 2008
4667 drw18
t
t
ENH
A
W
4