TSS461F-TDRZ-9 Atmel, TSS461F-TDRZ-9 Datasheet - Page 15

• Manufacturer Part Number: TSS461F-TDRZ-9
• Description: Network Controller & Processor ICs Van Data Link Controller
• Manufacturer: Atmel

Frame Examples
7615A–AUTO–02/06
The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is per-
formed before transmission.
However, since the CRC is calculated automatically from the identifier, command and data fields
by the TSS461F, the user should not be concerned with the circuit. When the frame check
sequence has been transmitted, the transmitting module must transmit an End Of Data (EOD)
sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to
terminate the transfer.
Figure 11. Acknowledge Sequences
The frames transmitted on the VAN bus are generated by several modules, each supplying dif-
ferent parts of the message. Figure 12 through Figure 15 show the four frame types specified in
the VAN standard, and what module is generating the different fields.
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The most straightforward frame is the normal data frame in Figure 13. Like all other frames it
is initiated with a SOF sequence. This sequence is generated by a bus master (not shown in
figure).
During this frame, there is basically only one module transmitting with the exception being
the acknowledgement, generated by the receiving module if requested in the RAK bit.
The reply request frame with immediate reply in Figure 13 is the only frame in which a slave
module can transmit data by filling it into the appropriate field.
The difference for the frame on the bus is that the R/W bit has changed state compared to
the normal frame.
This is a highly interactive frame where a bus master generates the SOF and the initiator
generates the identifier, the three first bits of the command, and the acknowledge. The RTR
bit, the data field, the frame check, the EOD and the EOF are all generated by the replying
module.
The reply request frame with deferred reply in Figure 14 is the same frame as the reply
request frame with immediate reply. But since the requested module does not generate the
RTR bit, the requesting module will continue with the frame check, the EOD and the EOF.
During this frame, the requested module will only generate the acknowledge, and only if this
was requested by the initiator through the RAK bit.
Finally, the deferred reply frame in Figure 16 which is sent when a module has prepared a
reply for a reply request that has been received earlier.
This frame is similar to the normal data frame with the exception being the R/W bit that has
changed state.
VAN BUS
SEQUENCE
VAN BUS
SEQUENCE
NUMBER OF
PRESCALED
CLOCKS
0
8
POSITIVE ACKNOWLEDGE
ABSENT ACKNOWLEDGE
16
24
32
TSS461F
15