TSS461F-TDRZ-9 Atmel, TSS461F-TDRZ-9 Datasheet - Page 24
TSS461F-TDRZ-9
Manufacturer Part Number
TSS461F-TDRZ-9
Description
Network Controller & Processor ICs Van Data Link Controller
Manufacturer
Atmel
Datasheet
1.TSS461F-TDRZ-9.pdf
(57 pages)
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Control and Status Registers
Line Control Register
(0x00)
CD[3:0] Clock Divider
PC Pulsed CodeOne
IVTX
IVRX
Transmit Control
Register (0x01)
24
TSS461F
•
•
•
They control the VAN Bus rate through a Baud Rate generator according to the formula below:
The TSS461F will transmit and receive data using the pulsed coding mode (i.e optical or radio
link mode). The use of this mode implies communication via the RXD0 input and the non-func-
tionality of the diagnosis system.
Zero: (default at reset) The TSS461F will transmit and receive data using the Enhanced
Manchester code (RXD0, RXD1, RXD2).
Invert TXD output.
Invert RXD inputs.The user can invert the logical levels used on either the TXD output or the
RXD inputs in order to adapt to different line drivers and receivers.
One: A one on either of these bits will invert the respective signals.
Zero: (default at reset). The TSS461F will set TXD to recessive state in Idle mode and consider
the bus free (recessive states on RXD inputs).
•
•
F
TSCLK
Read/write register.
Default value after reset: 0y00
reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this bit.
Read/Write register
Default value after reset: 0x02
=
F
------------------
n 16
XTAL1
MR3
MR3
×
7
7
MR2
MR2
6
6
MR1
MR1
5
5
MR0
MR0
4
4
VER2
VER2
3
3
VER1
VER1
2
2
VER0
VER0
1
1
7615A–AUTO–02/06
MT
MT
0
0
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