XRT83L38ES Exar, XRT83L38ES Datasheet - Page 49

• Manufacturer Part Number: XRT83L38ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.2
MICROPROCESSOR REGISTER TABLES
The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 8 byte
registers for independent programming and control. There are four additional registers for global control of all
channels and two registers for device identification and revision numbers. The remaining registers are for
factory test and future expansion. The control register map and the function of the individual bits are
summarized in
Channel 0 Control Registers
R
R
EGISTER
EG
0
1
2
3
. #
128 - 131
140 - 191
193 - 195
196 - 203
204 - 253
112 - 127
132 -139
16 - 31
32 - 47
48 - 63
64 - 79
80 - 95
96-111
0 - 15
192
254
255
00000000
00000001
00000010
00000011
Hex 0x00
Hex 0x01
Hex 0x02
Hex 0x03
A
N
DDRESS
UMBER
Table 17
R
T
R/W
R/W
R/W
R/W
YPE
EG
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
.
0xCC - 0xFD
0xC4 - 0xCB
0x8C - 0xBF
0xC1 - 0xC3
0x84 - 0x8B
INVQRSS_n
0x00 - 0x0F
0x20 - 0x2F
0x30 - 0x3F
0x40 - 0x4F
0x50 - 0x5F
0x60 - 0x6F
0x70 - 0x7F
0x80 - 0x83
0x10 -0x1F
RXTSEL_n
NLCDE1_n
Reserved
and
B
0xC0
0xFE
0xFF
HEX
IT
T
ABLE
7
Table 18
T
ABLE
R
18: M
TXTEST2_n
TXTSEL_n
NLCDE0_n
Reserved
EGISTER
B
17: M
IT
respectively.
6
ICROPROCESSOR
10000000 - 10000011
10000100 - 10001011
00000000 - 00001111
00010000 - 00011111
00100000 - 00101111
01000000 - 01001111
01010000 - 01011111
11000001 - 11000011
11000100 - 11001011
00110000 - 00111111
01100000 - 01101111
10001100 - 10111111
01110000 - 01111111
11001100 - 11111101
A
ICROPROCESSOR
DDRESS
TERSEL1_n
TXTEST1_n
CODES_n
RXON_n
B
11000000
11111110
11111111
BINARY
IT
5
46
TERSEL0_n
TXTEST0_n
R
RXRES1_n
EQC4_n
EGISTER
B
IT
R
4
EGISTER
Channel 0 Control Registers
Channel 1 Control Registers
Channel 2 Control Registers
Channel 3 Control Registers
Channel 4 Control Registers
Channel 5 Control Registers
Channel 6 Control Registers
Channel 7 Control Registers
Command Control registers for all 8 channels
R/W registers reserved for testing channels 0-3
Reserved
Command Control register for all 8 channels
Reserved
R/W registers reserved for testing channels 4-7
Reserved
Device “ID”
Device “Revision ID”
B
RXRES0_n
IT
JASEL1_n
EQC3_n
TXON_n
A
B
D
IT
DDRESS
ESCRIPTION
3
JASEL0_n
INSBPV_n
LOOP2_n
EQC2_n
B
IT
F
2
UNCTION
INSBER_n
LOOP1_n
EQC1_n
JABW_n
B
IT
XRT83L38
1
TRATIO_n
LOOP0_n
FIFOS_n
EQC0_n
B
IT
0