XRT83L38ES Exar, XRT83L38ES Datasheet - Page 83

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XRT83L38ES

Manufacturer Part Number
XRT83L38ES
Description
Peripheral Drivers & Components - PCIs
Manufacturer
Exar
Datasheet

Specifications of XRT83L38ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
REV. 1.0.2
MICROPROCESSOR INTERFACE I/O TIMING
I
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in
Figure 32
F
F
NTEL
IGURE
IGURE
R DY _D TAC K
AD D R[6:0]
DA TA[7:0]
W R _R/W
ALE_AS
I
R D _D S
NTERFACE
RCLK
RPOS
RNEG
29. R
30. I
or
C S
is described in
NTEL
ECEIVE
T
t
A
0
IMING
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SYNCHRONOUS
t
5
C
LOCK AND
t
1
- A
Table
SYNCHRONOUS
R EAD OPER ATIO N
Valid Address
51.
O
R
t
2
UTPUT
DY
P
ROGRAMMED
V alid Data for R eadback
D
ATA
T
IMING
I/O I
NTERFACE
80
R
HO
RCLK
T
t
0
IMING
t
5
R
t
3
D ata Available to W rite Into the LIU
RCLK
W RITE OPER ATIO N
V alid Address
t
4
F
Figure 30
XRT83L38
and

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