XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 28
XRT83SL30ES
Manufacturer Part Number
XRT83SL30ES
Description
Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
Manufacturer
Exar
Datasheet
1.XRT83SL30ES.pdf
(76 pages)
Specifications of XRT83SL30ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83SL30 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER
I
In Hardware mode, RXTSEL (Pin 44) can be tied “High” to select internal termination mode or tied “Low” to
select external termination mode. By default the XRT83SL30 is set for external termination mode at power up
or at Hardware reset.
In Host mode, bit 7 in the appropriate register,
page
F
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in
NTERNAL
IGURE
RNEG
TNEG
RPOS
TPOS
RCLK
TCLK
45), is set “High” to select the internal termination mode for the receive channel.
11. S
R
ECEIVE
IMPLIFIED
Line Driver
T
Equalizer
ERMINATION
TX
RX
D
IAGRAM FOR THE
M
ODE
T
ABLE
RXTSEL
R
R
int
int
0
1
6: R
I
NTERNAL
R
int
ECEIVE
(Table 19, “Microprocessor Register #1 bit description,” on
RRING
TRING
R
TTIP
RTIP
T
ECEIVE AND
25
ERMINATION
RX TERMINATION
0.68µF
EXTERNAL
INTERNAL
T
RANSMIT
C
ONTROL
1
4
5
8
1:2
1:1
T1
T2
T
ERMINATION
5
1
8
4
M
ODE
RTIP
RRING
TTIP
TRING
75 Ω, 100 Ω
110 Ω or 120 Ω
75 Ω, 100 Ω
110 Ω or 120 Ω
REV. 1.0.1
Table
7.
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