XRT83SL30ES Exar, XRT83SL30ES Datasheet - Page 59
XRT83SL30ES
Manufacturer Part Number
XRT83SL30ES
Description
Peripheral Drivers & Components - PCIs 1 CHT1/E1 LIUSH
Manufacturer
Exar
Datasheet
1.XRT83SL30ES.pdf
(76 pages)
Specifications of XRT83SL30ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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REV. 1.0.1
R
R
EGISTER
EGISTER
D6-D0
D6-D0
01001
01010
B
B
D7
D7
IT
IT
A
A
#
#
DDRESS
DDRESS
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
B6S2 - B0S2 Arbitrary Transmit Pulse Shape, Segment 2
B6S3 - B0S3 Arbitrary Transmit Pulse Shape, Segment 3
Reserved
Reserved
N
N
AME
AME
T
T
ABLE
ABLE
28: M
27: M
The shape of the transmitted pulse can be made user program-
mable by selecting "Arbitrary Pulse" mode, see
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the second time segment. B6S2 -B0S2 is in signed mag-
nitude format with B6S2 as the sign bit and B0S2 as the least
significant bit (LSB).
The shape of the transmitted pulse can be made user program-
mable by selecting "Arbitrary Pulse" mode, see
arbitrary pulse is divided into eight time segments whose com-
bined duration is equal to one period of MCLK.
This 7 bit number represents the amplitude of the arbitrary pulse
during the third time segment. B6S3 -B0S3 is in signed magni-
tude format with B6S3 as the sign bit and B0S3 as the least sig-
nificant bit (LSB).
ICROPROCESSOR
ICROPROCESSOR
56
R
R
EGISTER
EGISTER
F
F
UNCTION
UNCTION
#10
#9
BIT DESCRIPTION
BIT DESCRIPTION
Table 5
Table 5
. The
. The
R
R
XRT83SL30
EGISTER
EGISTER
T
T
R/W
R/W
R/W
R/W
YPE
YPE
R
V
R
V
ALUE
ALUE
ESET
ESET
0
0
0
0
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