XRT7295A/98ES-DS3 Exar, XRT7295A/98ES-DS3 Datasheet - Page 6

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XRT7295A/98ES-DS3

Manufacturer Part Number
XRT7295A/98ES-DS3
Description
Peripheral Drivers & Components - PCIs comeswith XRT7295A
Manufacturer
Exar
Datasheet

Specifications of XRT7295A/98ES-DS3

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
Line Termination and Input Capacitance
The recommended receive termination is shown in
Figure 3. The 75 resistor terminates the coaxial cable
with its characteristic impedance. The 0.01 F capaci-
tor to R
without disturbing the internally generated DC bias
level present on R
pin is 2.8pF.
TIMING RECOVERY
Output Jitter
The total jitter appearing on the RCLK output during
normal operation consists of two components. First,
XRT7295AE
IN
Rev. 2.0.0
couples the signal into the receive input
IN
. The input capacitance at the R
Figure 3. Receiver Configuration
IN
6
External Loop Filter Capacitor
Figure 3 shows the connection to an external 0.1 F
capacitor at the LPF1/LPF2 pins. This capacitor is part
of the PLL filter. A non-polarized, low-leakage capaci-
tor should be used. A ceramic capacitor with the value
0.1 F +/-20% is acceptable.
some jitter appears on RCLK because of jitter on the
incoming signal. (The following section discussed the
jitter transfer characteristic, which describes the rela-
tionship between input and output jitter.) Second, noise
sources within the XRT7295AE or noise sources that
are coupled into the device through the power supplies
create jitter on RCLK. The magnitude of this
XRT7295AE
XRT7295AE

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