MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 117

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

4.11.13 HSI Host Controller Timing Parameters
This section describes the timing parameters of the HSI Host Controller which are compliant with
High-speed Synchronous Serial Interface (HSI) Physical Layer specification version1.01.
4.11.13.1 Synchronous Data Flow
4.11.13.2 Pipelined Data Flow
4.11.13.3 Receiver Real-Time Data Flow
Freescale Semiconductor
First bit of
DATA
READY
FLAG
frame
Figure 76. Synchronized Data Flow READY Signal Timing (Frame and Stream Transmission)
First bit of
First bit of
DATA
DATA
FLAG
READY
FLAG
READY
frame
frame
Figure 77. Pipelined Data Flow Ready Signal Timing (Frame Transmission Mode)
A Ready can change
detected the start
detected the start
Receiver has
Receiver has
of the Frame
of the Frame
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
t
N-bits Frame
Figure 78. Receiver Real-Time Data Flow READY Signal Timing
NomBit
t
t
NomBit
NomBit
N-bits Frame
N-bits Frame
Last bit of
frame
B Ready shall not
change to zero
Last bit of
Last bit of
frame
frame
First bit of
frame
Receiver has captured a
Receiver has captured
and stored a complete
complete Frame
Frame
First bit of
First bit of
frame
frame
C. Ready can change
N-bits Frame
N-bits Frame
N-bits Frame
Last bit of
maintain zero of if
receiver does not
have free space
frame
D. Ready shall
Last bit of
Last bit of
frame
frame
Last bit of
change
Ready
Electrical Characteristics
frame
can
E.
F. Ready
maintain
its value
shall
can change
G. Ready
117