MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 86

• Manufacturer Part Number: MCIMX6S5DVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
Figure 45
the figure.
1
4.11.5.1.2
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
86
M1
M2
M3
M4
ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
ID
ENET_RX_DATA3,2,1,0
ENET_RX_CLK (input)
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
shows MII receive signal timings.
ENET_RX_EN
ENET_RX_ER
MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
(inputs)
Figure 45. MII Receive Signal Timing Diagram
Characteristic
Table 56. MII Receive Signal Timing
M1
1
Table 56
M2
describes the timing parameters (M1–M4) shown in
M3
Min.
35%
35%
5
5
M4
Max.
65%
65%
—
—
Freescale Semiconductor
ENET_RX_CLK period
ENET_RX_CLK period
Unit
ns
ns