MCIMX6S5DVM10AB Freescale Semiconductor, MCIMX6S5DVM10AB Datasheet - Page 90
MCIMX6S5DVM10AB
Manufacturer Part Number
MCIMX6S5DVM10AB
Description
Processors - Application Specialized i.MX6 Solo rev 1.1
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet
1.MCIMX6S5DVM10AB.pdf
(167 pages)
Specifications of MCIMX6S5DVM10AB
Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
256 kB
Operating Supply Voltage
1.175 V to 1.5 V
Mounting Style
SMD/SMT
Package / Case
FCBGA-624
Interface Type
I2C, I2S, SDIO, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
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Electrical Characteristics
90
1
2
3
4
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
For 10 Mbps and 100 Mbps, T
For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed
such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the
associated clock signal. For 10/100, the Max value is unspecified.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's
clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three
Tcyc of the lowest speed transitioned between.
Duty_G
Duty_T
Symbol
T
skewR
Tr/Tf
3
4
4
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Data to clock input skew at receiver
Duty cycle for Gigabit
Duty cycle for 10/100T
Rise/fall time (20–80%)
Table 61. RGMII Signal Switching Specifications
Figure 50. RGMII Transmit Signal Timing Diagram Original
cyc
will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
Description
1
Min.
45
40
—
(continued)
1
Max.
0.75
2.6
55
60
Freescale Semiconductor
Unit
ps
ns
%
%
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