E909.05A61DC ELMOS Semiconductor, E909.05A61DC Datasheet - Page 59

• Manufacturer Part Number: E909.05A61DC
• Description: Processors - Application Specialized Halios multipurpose sensor IC
• Manufacturer: ELMOS Semiconductor

Specifications of E909.05A61DC

• Rohs: yes
• Processor Series: EL16
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 8 MHz
• Data Ram Size: 3 kB
• Operating Supply Voltage: 2.25 V to 2.75 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Interface Type: I2C, SPI
• Memory Type: Flash, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

PRELIMINARY INFORMATION AUG 02, 2011
Register transmit data / receive data (0x00)
Table 6.14.1.2: transmit data / receive data
Register control (0x02)
Table 6.14.1.3: control
Register baud config (0x04)
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
ELMOS Semiconductor AG
Bit
Reset value
Internal access
External access R
Bit Description
Bit
Reset value
Internal access
External access R
Bit Description
Bit
Reset value
Internal access
External access R/W R/W Rv
HALIOS® MULTI-PURPOSE OPTICAL SENSOR WITH HIGH LIGHT IMMUNITY
15
0
R
8 : csb control (only for data transition and in master mode)
0 - byte mode
1 - keep csb active after related byte was transmitted
7:0 : transmit data / receive data
The 'send low water' interrupt will be cleared by writing a byte to the transmit data register
(FIFO).
The 'receive high water' interrupt will be cleared by reading a byte from the receive data
register (FIFO).
(see List Of All Interrupts)
15
0
R
14:12 : high water receive FIFO level
interrupt will be asserted when receive FIFO fill level increases to this value
default value: 2
10:8 : low water transmit FIFO level
interrupt will be asserted when transmit FIFO fill level decreases to this value
default value: 0
3 : slave
0 - master
1 - slave
2 : polarity: SSCPO, see SPI mode diagram
0 - clock off level 0
1 - clock off level 1
1 : phase: SSCPH, see SPI mode diagram
0 - 1st edge shift, 2nd edge sample
1 - 1st edge sample, 2nd edge shift
0 : order
0 - LSB first
1 - MSB first
15
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
14
0
R
R
14
0
R/W R/W R/W R
R/W R/W R/W R
14
0
13
0
R
R
13
1
13
0
12
0
R
R
12
0
12
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
11
0
R
R
11
0
11
0
Data Sheet 59 / 67
10
0
R
R
10
0
R/W R/W R/W R
R/W R/W R/W R
10
0
9
0
R
R
9
0
9
0
8
0
(R)
W
(R)
W
8
0
8
0
7
0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
7
0
7
0
6
0
6
0
R
R
6
0
5
0
5
0
R
R
5
0
4
0
4
0
R
R
4
0
QM-No.: 25DS0014E.00
3
0
3
1
R/W R/W R/W R/W
R/W R/W R/W R/W
3
0
2
0
2
0
2
1
E909.05
1
0
1
0
1
0
0
0
0
1
0
0