79RC32H434-300BC IDT, 79RC32H434-300BC Datasheet - Page 18

• Manufacturer Part Number: 79RC32H434-300BC
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32H434-300BC

• Part # Aliases: IDT79RC32H434-300BC

IDT RC32434
Note: For a diagram showing the COLD Reset Operation with Internal Boot Configuration Vector, see Figure 3.6 in the RC32434 User
Reference Manual.
MADDR[21:16]
MADDR[15:0]
1.
2.
3.
4.
5.
6.
7.
COLDRSTN
*
EXTBCV
COLDRSTN sampled negated (high) by the RC32434
EXTCLK
EXTBCV is asserted (i.e., pulled-up). COLDRSTN is asserted by external logic. The RC32434 responds by immediately tri-stating the bottom
16-bits of the memory and peripheral address bus (MADDR[15:0]), driving the remaining address bus signals (i.e., MADDR[21:16]), and
asserting RSTN. EXTCLK is undefined at this point.
External logic drives the boot configuration vector on MADDR[15:0].
External logic negates COLDRSTN and tri-states the boot configuration vector on MADDR[15:0]. In response, the RC32434 stops sampling
the boot configuration vector and retains the boot configuration vector value seen two clock cycles earlier (i.e., the value on the MADDR[15:0]
lines two rising edges of CLK earlier). Within 16 CLK clock cycles after COLDRSTN is sampled negated, the RC32434 begins driving
MADDR[15:0].
The RC32434 waits for the PLL to stabilize.
The RC32434 then begins generating EXTCLK.
After at least 4000 CLK clock cycles, the RC32434 tri-states RSTN.
At least 4000 CLK clock cycles after negating RSTN, the RC32434 samples RSTN. If RSTN is negated, cold reset has completed and the
RC32434 CPU begins executing by taking MIPS reset exception.
Figure 4 COLD Reset Operation with External Boot Configuration Vector AC Timing Waveform
RSTN
CLK
1
2
Boot Configuration Vector
Driven
3
*
18 of 53
4
clock cycles
4000 CLK
Driven
5
clock cycles
4000 CLK
6
January 19, 2006