MCIMX251AJM4AR2 Freescale Semiconductor, MCIMX251AJM4AR2 Datasheet
MCIMX251AJM4AR2
Specifications of MCIMX251AJM4AR2
Related parts for MCIMX251AJM4AR2
MCIMX251AJM4AR2 Summary of contents
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... Bluetooth™ connectivity for hands free phone calling and streaming audio from wireless devices like phones or PND © 2012 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX25AEC Rev. 9, 06/2012 MCIMX25 Package Information Plastic package Case 5284 mm, 0 ...
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... On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY. • Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included. • i.MX25 only supports Little Endian mode. i.MX25 Applications Processor for Automotive Products, Rev Freescale Semiconductor ...
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... Touchscreen CSI FlexCAN (2) ESAI SIM (2) Security 10/100 Ethernet HS USB 2.0 OTG + PHY HS USB 2.0 Host + PHY 12-bit ADC SD/SDIO/MMC (2) i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 1. Ordering Information Projected Silicon Temperature Version Range ( C) 1.1 – mm, 0.8 mm pitch, MAPBGA-400 1.1 – mm, 0 ...
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... Table 2. i.MX25 Parts Functional Differences (continued) Features External Memory Controller (3) SSI/I2S (2) CSPI (2) UART (5) i.MX25 Applications Processor for Automotive Products, Rev MCIMX251 Yes Yes Yes Yes Yes MCIMX255 Yes Yes Yes Yes Yes Freescale Semiconductor ...
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... SPBA Shared Domain SDMA Peripherals UART(3) CSPI(2) ADC/TSC Audio/Power Management Figure 1. i.MX25 Simplified Interface Block Diagram i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Ext. Graphics NAND Camera LCD Display 1 Accelerator Flash Sensor ARM ® Processor Domain (AP) LCDC / CSI CSI ...
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... M3IF provides arbitration between multiple masters requesting access to the external memory. • Enhanced SDRAM/LPDDR memory controller (ESDCTL) interfaces to DDR2 and SDR interfaces. • NAND Flash controller (NFC) provides an interface to NAND Flash memories. • Wireless External Interface Memory controller (WEIM) interfaces to NOR Flash and PSRAM. Brief Description Freescale Semiconductor ...
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... Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Brief Description Each Enhanced Periodic Interrupt Timer (EPIT 32-bit set-and-forget timer that starts counting after the EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention ...
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... The SIM supports only 11 and 12ETU cards and can communicate at the default rate, which is obtained at Fi/Di=372/1. An external companion controller is required to support cards aligned on 10.8 or 11.8ETU and to support other rates, such as those obtained at Fi/Di=372/2 and Fi/Di=372/4. The System JTAG Controller (SJC) provides debug and test control with maximum security. Freescale Semiconductor ...
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... The SSI is a full-duplex serial port that allows the processor to communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the inter-IC sound bus standard (I2S). The SSIs interface to the AUDMUX for flexible audio routing. ...
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... Determines the reference current for the USB PHY1 bandgap reference. An external resistor to GND is required. USBPHY2_DM The output impedance of these signals is expected recommended to also have on-board 33 USBPHY2_DP series resistors (close to the pins). i.MX25 Applications Processor for Automotive Products, Rev Table 4. Signal Considerations (continued) Description Freescale Semiconductor ...
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... DC recommended operating conditions. Parameter Core supply voltage (at 266 MHz) Core supply voltage (at 400 MHz) 1 Coin battery BAT_VDD I/O supply voltage, GPIO NFC,CSI,SDIO i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor CAUTION Table 5 may cause permanent Table 5. DC Absolute Maximum Ratings Symbol DDIOmax ...
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... DD_MDDR NV 1.75 — DD_DDR2 NV 1.75 — DD_SDRAM V 3.17 3.3 DD_usbphy1 V 3.0 3.3 DD_usbphy2 V 3.0 3.3 DD_OSC24M V 1.4 — DD_PLL V 3.0 3.3 DD_tsc Vref 2 DD_tsc FUSEV 3.3 ± 5% — DD (program mode) V 1.0 — DD_ T –40 — A can be connected to DD_BAT Table 7 Freescale Semiconductor Max. Units 3.6 — 1.95 V 1.9 V 3.6 V 3.43 V 3.6 V 3.6 V 1. DD_tsc 3 for current ...
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... Table 10. Recommended External Reference Clock Specifications Voh Vol Frequency Tolerance Trise i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Symbol I program I read ). program Table 8. Interface Frequency Limits Min ...
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... Rx 21.5 — Tx 33.8 — — 0.6 Rx 120 — — Rx 252 — Tx 5.5 — 50 100 1 Stop/Sleep Run (266 MHz) Run (400 MHz) — Active @ 266 MHz On Off Off On Off On Off Off On Freescale Semiconductor Unit Active @ 400 MHz Off ...
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... In this low-power mode, i.MX25 cannot be woken up with an interrupt; it must be powered back up before it can detect any events. Table 14. iMX25 Reduced Power Mode Current Consumption Power Group Power Supply BAT_VDD BAT_VDD i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Current Consumption for Power Modes Voltage Setting Doze Wait 3 ...
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... There minimum time between supplies coming up, and minimum time between POR_B assert and de-assert. • The dV/dT should be no faster than 0. for all power supplies, to avoid triggering ESD circuit. i.MX25 Applications Processor for Automotive Products, Rev CAUTION NOTE NOTE Freescale Semiconductor ...
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... USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC, OSC24M_VDD, MPPLL_VDD, UPLL_VDD, and FUSEVDD (FUSEVDD is tied to GND if fuses are not programmed) for not less than 1 ms and not more than 32 ms, after NVCCx reaches 90% of 3.3 V. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Figure 2. Power-Up Sequence Diagram NOTE 17 ...
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... Power Supply QVDD NVCC_EMI1, NVCC_EMI2 NVCC_CRM, NVCC_SDIO, NVCC_CSI, NVCC_NFC, NVCC_JTAG, NVCC_LCDC, NVCC_MISC MPLL_VDD, UPLL_VDD USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD, NVCC_ADC i.MX25 Applications Processor for Automotive Products, Rev NOTE NOTE NOTE Table 15. Power Consumption Voltage (V) 1.52 1.9 3.6 1.65 3.3 Max Current (mA) 360 30 110 20 40 Freescale Semiconductor ...
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... Flag: Trace style with ground balls under the die connected to the flag • Die Attach: 0.033 mm non-conductive die attach 0.3 W/m K • Mold compound: Generic mold compound 0.9 W/m K i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 15. Power Consumption (continued) Voltage (V) 3.6 1.55 Table 12, for more details on the power modes ...
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... Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection NOTE Symbol Value Unit R 55 °C/W eJA R 33 °C/W eJA R 46 °C/W eJMA R 29 °C/W eJMA R 22 °C/W eJB R 13 °C/W eJCtop 2 °C/W JT Freescale Semiconductor ...
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... DC I/O parameters for SDRAM. Table 18. SDRAM DC Electrical Characteristics DC Electrical Characteristics High-level output voltage Low-level output voltage High-level output current Low-level output current High-level DC input voltage i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Symbol Test Conditions Voh I = –1mA OVDD – 0. Specified Drive 0 ...
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... OVDD/2 – 0.125 — OVDD + 0.3 — OVDD+0.6 OVDD/2 OVDD/2 + 0.04 — — 110 60 — — 980 — — 1210 between OVDD and OVDD-0.28 V. out between 0 V and 280 mV. Simulation circuit out Freescale Semiconductor Units Units ...
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... Pull-up resistor (47 k PU) Pull-up resistor (100 k PU) Pull-down resistor (100 k PD) Input current (no pull-up/down) Input current (22 k PU) i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Symbol Test Conditions Voh Ioh=–1mA OVDD – 0.15 Ioh = Specified Drive Vol Iol=1mA Iol=Specified Drive I Voh=0 ...
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... OVDD 80% 20% 0V PA1 Freescale Semiconductor ...
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... Output (at pad) Figure 5. Output Pad Propagation and Transition Time Waveform signal “1” pdat from core signal “0” pdat from core signal open from core Output (at pad) i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 50% tPLH 80% 50% 20% tTLH 50% ...
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... 1.65–1. 1.65–1. tpo 3.0–3 3.0–3 1.65–1. 1.65–1.95 V tpo 3.0–3 3.0–3 1.65–1. 1.65–1. Min. Typ. Max. Rise/Fall Rise/Fall Rise/Fall 40 — 60 0.95/0.84 1.36/1.11 2.06/1.60 1.58/1.37 2.19/1.77 3.20/2.47 2.70/2.50 1.80/1.40 3.01/2.37 3.40/3.20 2.80/2.14 4.63/3.38 1.60/1.39 2.23/1.79 3.26/2.50 2.94/2.51 4.05/3.17 5.72/4.27 1.85/1.48 2.90/2.17 4.75/3.43 2.93/2.37 4.56/3.40 7.33/5.26 3.07/2.62 4.22/3.30 6.03/4.48 5.82/4.95 7.94/6.19 11.28/8.28 3.04/2.47 4.73/3.50 3.01/2.36 5.37/4.40 7.70/8.10 4.63/3.38 1.92/2.1 2.96/2.96 4.47/4.38 2.44/2.53 3.7/3.64 5.54/5.31 2.05/2.27 3.32/3.67 5.27/5.85 2.71/2.84 4.39/4.51 7.00/7.15 2.35/2.49 3.58/3.61 5.35/5.24 3.31/3.43 4.9/4.786 7.19/6.8 2.58/2.69 4.17/4.27 6.64/6.74 3.62/3.60 5.86/5.61 9.34/8.76 3.39/3.51 5.03/4.89 7.39/6.95 5.28/5.35 7.6/7.14 10.97/9.45 3.71/3.68 6.03/5.75 9.64/8.97 5.52/5.32 8.80/7.96 13.9/11.3 1.942/2.04 2.923/2.95 4.33/4.3 2.378/2.48 3.541/3.53 5.29/5.09 2.03/2.28 3.19/3.59 4.97/5.64 2.59/2.73 4.10/4.33 6.43/6.77 2.29/2.44 3.42/3.49 5.05/5.02 3.05/3.20 4.46/4.45 6.53/6.3 2.45/2.62 3.86/4.07 6.02/6.35 3.36/3.39 5.34/5.22 8.40/8.08 3.12/3.26 4.58/4.53 6.69/6.42 4.60/4.73 6.61/6.32 9.5/8.32 3.43/3.46 5.48/5.34 8.65/8.26 4.89/4.79 7.75/7.16 12.2/9.97 Freescale Semiconductor Units % ...
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... Output pad slew rate (max. drive) 2 Output pad slew rate (high drive) 2 Output pad slew rate (standard drive) i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Test Capacitance tpv 3.0–3 3.0–3 1.65–1. 1.65–1. tpv 3.0– ...
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... Min. Typ. Max. Rise/Fall Rise/Fall Rise/Fall 0.82/0.47 1.1/0.76 1.6/1.04 0.74/1 1.1/1.5 1.75/2.16 1.1/1.3 1.43/1.6 2/2 1.75/1.63 2.67/2.22 2.92/3 1.62/1.28 1.9/1.56 2.38/1.82 1.82/1.55 2.28/1.87 2.95/2.54 1.88/2.1 2.2/2.4 2.7/2.75 2.4/2.6 3/3.07 3.77/3.71 0.16/0.12 0.23/0.18 0.33/0.29 0.16/0.13 0.22/0.18 0.33/0.29 — — 25 Freescale Semiconductor Units mA / ...
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... Output enable to output valid delay (standard drive), 40%–60% 2 Output pad slew rate (max. drive) 2 Output pad slew rate (high drive) 2 Output pad slew rate (standard drive) i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Test Min. Symbol Condition Rise/Fall Fduty — 40 tpr 25 pF 0.88/0. ...
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... V (continued) – Min. Max. Typ. Rise/Fall 7 43 112 7 46 118 0.74/1 1.1/1.5 1.75/2.16 2.67/2.22 2.92/3 2.28/1.87 2.95/2.54 2.4/2.6 3/3.07 3.77/3.71 0.30/0.18 0.33/0.29 0.30/0.18 0.33/0.29 — — 25 3.6 V – Min. Max. Typ. Rise/Fall 40 60 1.12/2.51 1.64/1.32 1.60/2.39 2.84/2.10 1.43/1.16 2.05/1.60 2.66/2.09 3.70/2.80 2.09/1.67 3.00/2.30 3.40/3.09 5.56/4.12 1.74/1.73 2.67/2.52 2.39/2.32 3.58/3.33 Freescale Semiconductor Units mA/ns mA/ns mA/ Units % ...
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... Input Pad Propagation Delay without Hysteresis, 4 50%–50% Input Pad Propagation Delay with Hysteresis, 4 50%–50% Input Pad Propagation Delay without Hysteresis, 4 40%–60% i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor tpo tpo tpo ...
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... V (continued) – 1.353/1.457 1.637/1.659 2.163/1.991 0.16/0.12 0.23/0.18 0.33/0.29 0.16/0.13 0.22/0.18 0.33/0.29 — — — Min. Max. Typ. Rise/Fall Rise/Fall — — 133 0.52/0.51 0.79/0.72 1.25/1.09 0.98/0.96 1.49/1.34 2.31/1.98 1.13/1.10 1.74/1.55 2.71/2.30 2.15/2.10 3.28/2.92 5.11/4.31 2.26/2.19 3.46/3.07 5.39/4.56 4.30/4.18 6.59/5.79 10.13/8.55 0.80/1.03 1.36/1.50 2.21/2.40 1.06/1.32 1.76/1.90 2.83/2.82 1.04/1.27 1.74/1.83 2.79/2.70 1.63/1.90 2.63/2.69 4.18/3.86 1.55/1.80 2.53/2.57 4.03/3.76 2.72/3.06 4.31/4.29 6.80/6.19 0.80/0.91 1.44/1.59 2.24/2.29 1.06/1.12 1.76/1.91 2.74/2.75 Freescale Semiconductor Units % MHz ...
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... Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from pad (20%–80%). i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Load Symbol ...
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... Max. Typ. Units Rise/Fall — 133 MHz 0.79/0.72 1.25/1.09 ns 1.49/1.34 2.31/1.98 1.74/1.55 2.71/2.30 ns 3.28/2.92 5.11/4.31 3.46/3.07 5.39/4.56 ns 6.59/5.79 10.13/8.55 1.97/1.83 2.98/2.78 ns 2.37/2.23 3.57/3.37 2.34/2.20 3.54/3.33 ns 3.22/3.08 4.85/4.65 3.11/2.96 4.70/4.50 ns 4.86/4.72 7.33/7.12 2.13/2.00 3.14/2.94 ns 2.53/2.40 3.74/3.54 2.51/2.37 3.70/3.50 ns 3.38/3.24 5.02/4.82 3.27/3.13 4.87/4.66 ns 5.02/4.88 7.49/7.29 1.91/1.81 3.10/2.89 ns 2.31/2.20 3.72/3.47 2.28/2.18 3.69/3.43 ns 3.18/3.04 5.08/4.69 3.09/2.94 4.95/4.55 ns 4.88/4.66 7.73/7.05 2.00/1.90 3.14/2.93 ns 2.32/2.21 3.64/3.41 2.28/2.19 3.60/3.36 ns 2.99/2.87 4.69/4.36 2.92/2.79 4.5894.25 ns 4.34/4.16 6.79/6.24 0.64/0.79 1.14/1.36 V/ns 0.52/0.61 0.90/1.02 Freescale Semiconductor ...
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... AC requirements for mobile DDR I/O. Table 26. AC Requirements for Mobile DDR I/O Parameter AC input logic high AC input logic low AC differential input voltage AC differential cross point voltage for input i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Load Symbol Condition tps tps ...
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... Min. Max. Typ. Units Rise/Fall Rise/Fall — — 133 MHz 0.82/0.87 1.14/1.13 1.62/1.50 1.56/1.67 2.13/2.09 3.015/2.7 7 1.23/1.31 1.71/1.68 2.39/2.22 2.31/2.47 3.22/3.12 4.53/4.16 2.44/2.60 3.38/3.27 4.73/4.38 4.65/4.99 6.38/6.23 9.05/8.23 0.97/1.19 1.69/0.75 2.17/2.46 2.85/3.21 2.02/2.30 2.93/3.27 1.15/1.39 1.72/1.93 2.51/2.77 3.57/3.91 2.54/2.85 3.66/3.97 2.01/1.57 2.45/2.69 3.54/3.77 5.73/6.05 4.10/4.51 5.84/6.13 1.06/1.26 1.53/1.73 2.18/2.47 1.38/1.38 1.96/2.23 2.78/3.12 1.15/1.20 1.72/1.93 2.45/2.71 1.75/1.67 2.37/2.66 3.35/3.67 1.91/2.01 2.30/2.52 3.26/3.50 2.88/2.56 3.59/3.97 5.06/5.36 0.90/1.27 1.44/1.89 2.19/2.87 1.07/1.77 1.66/2.51 2.51/3.69 1.01/1.48 1.58/2.16 2.38/3.23 1.37/2.33 2.06/3.09 3.06/4.46 1.32/2.14 2.02/3.00 3.01/4.36 2.04/3.67 3.00/4.91 4.40/6.90 1.03/1.34 1.54/1.94 2.26/2.88 1.16/1.74 1.74/2.44 2.55/3.54 1.11/1.51 1.65/2.15 2.43/3.16 1.39/2.10 2.03/2.89 2.95/4.13 1.35/2.03 1.99/2.83 2.89/4.03 1.91/3.23 2.76/4.30 3.98/6.01 1.11/1.20 1.74/1.75 2.42/2.46 V/ns 0.97/0.65 0.92/0.94 1.39/1.30 0.76/0.80 1.16/1.19 1.76/1.66 V/ns 0.40/0.43 0.61/0.63 0.93/0.87 Freescale Semiconductor % ...
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... Output pad propagation delay (standard drive), 50%–50% input signals and crossing of output signals 1 Output pad propagation delay (max. drive), 40%–60% input signals and crossing of output signals i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Load Symbol Condition tps tdit ...
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... Min. Max. Typ. Units Rise/Fall Rise/Fall 1.85/1.75 2.65/2.49 3.79/3.55 2.52/2.42 3.51/3.36 4.97/4.72 2.42/2.32 3.40/3.25 4.83/4.59 3.76/3.66 5.15/4.99 7.17/6.92 1.37/1.34 2.22/2.02 3.53/3.12 1.77/1.83 2.77/2.63 4.30/3.92 1.55/1.56 2.46/2.30 3.87/3.47 2.15/2.29 3.28/3.21 5.02/4.67 2.07/2.18 3.20/3.08 4.92/4.50 3.28/3.65 4.84/4.90 7.21/6.89 1.46/1.42 2.28/2.07 3.54/3.13 1.77/1.81 2.71/2.56 4.15/3.78 1.60/1.59 2.47/2.30 3.82/3.41 2.07/2.18 3.12/3.02 4.72/4.37 2.01/2.09 3.05/2.91 4.64/4.23 2.96/3.26 4.34/4.37 6.45/6.13 1.11/1.20 1.74/1.75 2.63/2.48 V/ns 0.60/0.65 0.93/0.95 1.39/1.29 0.75/0.81 1.16/1.18 1.76/1.65 V/ns 0.40/0.43 0.62/0.64 094/0.87 0.38/0.41 0.59/0.61 0.89/0.83 V/ns 0.20/0.22 0.31/0.32 0.47/0.43 89 202 435 mA/ns 95 213 456 60 135 288 mA/ns 63 142 302 29 67 144 mA/ 150 0.07/0.08 0.11/0.12 0.16/0.20 0.56/0.69 0.87/1.08 1.37/1.62 1.38/1.51 1.68/1.89 2.18/2.42 Freescale Semiconductor ...
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... Parameter Duty cycle Clock frequency 1 Output pad transition times 1 Output pad propagation delay , 50%–50% input signals and crossing of output signals i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 29. AC Parameters for DDR2 I/O Load Symbol Condition Fduty — f — tpr ...
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... OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) Min. Max. Typ. Rise/Fall Rise/Fall 1.47/1.38 2.13/2.00 3.072/2.87 1.75/1.67 2.54/2.40 3.65/3.45 1.32/1.28 2.11/2.00 3.31/3.12 1.66/1.65 2.61/2.50 4.06/3.81 1.40/1.37 2.16/2.06 3.30/3.13 1.67/1.66 2.56/2.45 3.89/3.67 0.86/0.98 1.35/1.5 2.15/2.19 0.46/054 0.72/0.81 1.12/1.16 72 172 400 77 183 422 0.07/0.08 0.10/0.12 0.17/0.20 0.89/0.87 1.41/1.37 2.16/2.07 1.71/1.69 2.22/2.18 2.98/2.88 Max. OVDD + 0.3 OVDD/2 – 0.25 0.5 OVDD + 0.6 OVDD/2 + 0.175 OVDD/2 + 0.125 Freescale Semiconductor Units V/ns mA/ Units ...
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... Table 33. WR0 Sequence Timing Parameters ID Parameter OW5 Write 0 Low Time OW6 Transmission Time Slot i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor OW1 Figure 7. 1-Wire RPP Timing Diagram Symbol t RSTL t PDH t PDL t RSTH Table 33 describes the timing parameters (OW5– ...
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... Applications Processor for Automotive Products, Rev OW8 OW7 Figure 9. Write 1 Sequence Timing Diagram OW8 OW7 OW9 Figure 10. Read Sequence Timing Diagram Table 34. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT t RELEASE Table 34 describes the timing Min. Typ. Max. Units 117 120 15 — 45 Freescale Semiconductor ...
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... Maximum difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) tskew6 Maximum difference in cable propagation delay without accounting for ground bounce i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 35. Timing Parameters Description Value/Contributing Factor Peripheral clock frequency ...
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... T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew6) T – (tsu + thi) T > tsu + thi + tskew3 + tskew4 trd1 Table 36 Adjustable Parameter time_1 time_2r time_9 If not met, increase time_2 — time_ax time_pio_rdx time_1, time_2r, time_9 Freescale Semiconductor ...
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... Avoid bus contention when switching buffer off by making toff long enough 1 See Figure 12. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor t1 t2w ton tB tA Figure 12. PIO Write Mode Timing Relation T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew5) T – ...
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... DMARQ ADDR (See note 1) DMACK buffer_en DIOW Write Data(15:0) i.MX25 Applications Processor for Automotive Products, Rev tgr tfr Figure 13. MDMA Read Mode Timing tm ton td1 tk td Figure 14. MDMA Write Mode Timing tk1 tkjn tk1 tkjn toff Freescale Semiconductor ...
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... Ultra DMA (UDMA) Mode Timing UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in- and out-transfers are provided. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Relation T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew6) T – ...
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... DATA READ DATA WRITE buffer_en Figure 16. Timing for Host-Terminated UDMA In-Transfer i.MX25 Applications Processor for Automotive Products, Rev tack tenv tds trp tc1 tc1 tx1 tds tdh tc1 tc1 tdh tack tmli tmli tzah ton tdzfs tcvh toff tzah Freescale Semiconductor ...
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... There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. Make t and t big enough to avoid bus contention. on off i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor tli5 tc1 tc1 tss1 tds tdh Table 39 ...
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... DIOR DATA WRITE IORDY buffer_en Figure 19. Timing for Host-Terminated UDMA Out-Transfer i.MX25 Applications Processor for Automotive Products, Rev tack tenv tcyc ton tdzfs tdvs tdvh tdvs tli1 tss tcyc tli2 tcyc1 tdzfs_mli tli3 tcyc trfs1 tack tcvh toff Freescale Semiconductor ...
Page 51
... Smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats). The following subsections describe the CSI timing in gated and ungated clock modes. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 40. Value T) – ...
Page 52
... Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge VSYNC HSYNC PIXCLK DATA[15:0] Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge i.MX25 Applications Processor for Automotive Products, Rev Table 41 describes the timing Freescale Semiconductor ...
Page 53
... CSI DATA setup time P3 CSI DATA hold time P4 CSI pixel clock high time P5 CSI pixel clock low time P6 CSI pixel clock frequency i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Symbol tV2H tHsu tDsu tDh tCLKh tCLKl fCLK Table 42 P1 ...
Page 54
... SS n (input) t6’ SCLK (input) t10 t11 MISO t12 t13 MOSI Figure 24. CSPI Slave Mode Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev t2’ t1’ Table t7’ t5’ t3’ t14 t4 t4 t14 Freescale Semiconductor ...
Page 55
... The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash controller (NFC), and wireless external interface module (WEIM). The following subsections give timing information for these submodules. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 43. CSPI Interface Timing Parameters Symbol t ...
Page 56
... SD1 SD4 SD5 SD4 SD5 SD5 SD7 COL/BA SD8 SD10 SD9 Data SD4 Note: CKE is high during the read/write cycle. SD5 Parameter 1 1 SD2 SD3 Symbol Min. Max. tCH 3.4 4.1 tCL 3.4 4.1 tCK 7.5 — tCMS 2.0 — tCMH 1.8 — Freescale Semiconductor Unit ...
Page 57
... Table 49. SDCLK SDCLK CS RAS CAS SD4 WE SD6 ADDR BA DQ DQM Figure 26. SDR SDRAM Write Cycle Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Parameter SD1 SD3 SD11 SD5 SD12 SD7 ROW / BA Symbol Min. Max. tAS 2.0 — tAH 1.8 — ...
Page 58
... Figure 27. SDRAM Refresh Timing Diagram Symbol Min. Max. tCH 3.4 4.1 tCL 3.4 4.1 tCK 7.5 — tCMS 2.0 — tCMH 1.8 — tAS 2.0 — tAH 1.8 — tRP 1 4 tRCD 1 8 tDS 2.0 — tDH 1.3 — SD2 SD3 SD10 ROW/BA Freescale Semiconductor Unit clock clock ns ns ...
Page 59
... CAS WE ADDR BA CKE Don’t care Figure 28. SDRAM Self-Refresh Cycle Timing Diagram The clock continues to run unless CKE is low. Then the clock is stopped in low state. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Symbol tCH tCL tCK tAS tAH 1 tRP 1 ...
Page 60
... SD18 SD17 Data Data Data Data SD17 SD18 Parameter Min. Max. Unit 1.8 — SD20 SD19 SD18 Data Data Data Data SD18 1 Symbol Min. Max. tDS 0.95 — tDH 0.95 — tDSS 1.8 — tDSH 1.8 — Freescale Semiconductor ns Unit ...
Page 61
... ID SD21 DQS – DQ Skew (defines the data valid window in read cycles related to DQS) SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor SD22 SD21 Data Data Data ...
Page 62
... SDRAM clock cycle time i.MX25 Applications Processor for Automotive Products, Rev DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Table Parameter DDR2 51, “tlS, tlH Derating Values for DDR2-400 Symbol Min. Max. t 0.45 0. 0. Freescale Semiconductor Unit ...
Page 63
... Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Parameter CK, CK Differential Slew Rate 1.5 V/ns tlH tlS +94 +217 +124 +89 +209 +119 +83 +197 +113 +75 +180 +105 +45 +155 +75 +21 +113 +51 0 +30 +30 – ...
Page 64
... DM DM DDR18 DDR2-400 Symbol Min. Max. t 0.025 — DS1(base) t 0.025 — DH1(base) t 0.2 — DSS t 0.2 — DSH t -0.25 0.25 DQSS t 0.35 — DQSH t 0.35 — DQSL Table 53, “DtDS1, 1,2,3 0.7 V/ns 0.6 V/ns 0.5 Vns Freescale Semiconductor Unit ns ns tCK tCK tCK tCK tCK 0.4 V/ ...
Page 65
... DDR26 DQS output access time from SDCLK posedge 1 Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor DQS Single-Ended Slew Rate 63 — — ...
Page 66
... NFALE NFIO[7:0] Figure 35. Address Latch Cycle Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 34 through NF4 Freescale Semiconductor ...
Page 67
... Figure 37. Read Data Latch Cycle Timing Diagram ID Parameter NF1 NFCLE setup time NF2 NFCLE hold time NF3 NFCE setup time NF4 NFCE hold time i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
Page 68
... N/A tDHR N/A NOTE Table 56 describes the timing parameters Example Timing for NFC Clock 33 MHz Unit Min. Max. 28 — — — — 27.5 ns 620 — — — ns 12.5 — — — ns Freescale Semiconductor ...
Page 69
... BCLK high-level width WE4 Clock fall to address valid WE5 Clock rise/fall to address invalid WE6 Clock rise/fall to CS[x] valid WE7 Clock rise/fall to CS[x] invalid i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor WEIM Output Timing WE1 WE2 ... WE4 WE6 WE8 WE10 WE12 WE14 ...
Page 70
... Applications Processor for Automotive Products, Rev (continued) Parameter NOTE Min. Max. Unit 3 — ns 1/2 BCLK — ns +2.63 6.9 — — ns 2.4 — — ns 7.2 — — — ns 5.4 — ns –3.2 — ns Freescale Semiconductor ...
Page 71
... Figure 39. Synchronous Memory Timing Diagram for Read Access—WSC=1 BCLK Last Valid Address ADDR CS[x] RW LBA OE EB[y] DATA Figure 40. Synchronous Memory Timing Diagram for Write Access— i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 56 for specific control parameter settings. WE4 V1 WE6 WE14 WE10 WE12 WE19 WE4 V1 ...
Page 72
... Figure 41. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses— i.MX25 Applications Processor for Automotive Products, Rev WE5 Address V1 WE15 WE24 WE24 WE22 WE22 WE19 WE19 V1 V1+2 Halfword Halfword WE18 WE18 WSC=2, SYNC=1, DOL=0 Address V2 WE7 WE11 WE13 V2 V2+2 Halfword Halfword Freescale Semiconductor ...
Page 73
... Last Valid Addr M_DATA WE6 CS[x] WE8 RW WE14 LBA OE WE12 EB[y] Figure 43. Muxed A/D Mode Timing Diagram for Synchronous Write Access— i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Address V1 WE15 WE24 WE22 WE17 V1 WE16 BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 WE5 Address V1 Write WE15 ...
Page 74
... Applications Processor for Automotive Products, Rev WE5 Address V1 WE14 WE15 WE10 WSC=7, LBA=1, LBN=1, LAH=1, OEA=7 Table 57 help to determine timing parameters relative to chip select (CS) WE31 Address V1 WE39 WE35 WE37 V1 WE43 WE20 Read Data WE18 WE7 WE11 WE13 WE32 Next Address WE40 WE36 WE38 WE44 Freescale Semiconductor ...
Page 75
... LBA OE EB[y] MAXCO Figure 46. Asynchronous A/D Muxed Read Access (RWSC = 5) CS[x] ADDR Last Valid Address RW LBA OE EB[y] DATA Figure 47. Asynchronous Memory Write Access i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor MAXDI WE31 Addr. V1 WE32A WE40 WE39 WE35A WE37 WE31 Address V1 WE33 WE39 WE45 D(V1) ...
Page 76
... Synchronous Measured 1 Parameters 2 WE4 – WE6 – CSA 3 WE7 – WE5 – CSN WE41 D(V1) WE42 WE34 WE46 WE42 WE32 Next Address WE40 WE36 WE38 WE44 WE48 Max Min (If 133 MHz is supported by SoC) — 3 – CSA — 3 – CSN Freescale Semiconductor Unit ns ns ...
Page 77
... CS[x] Valid to EB[y] Valid (Write access) WE46 EB[y] Invalid to CS[x] Invalid (Write access) WE47 DTACK Valid to CS[x] Invalid WE48 CS[x] Invalid to DTACK invalid i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Determination By Synchronous Measured 1 Parameters WE4 – WE7 + (LBN + LBA + 1 –3 + (LBN + LBA + 2 – CSA ) WE8 – WE6 + (RWA – CSA) WE7 – ...
Page 78
... DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. All configuration parameters (CSA, CSN, EBWA, EBWN, LBA, LBN, LAH, OEN, OEA, EBRA, and EBRN) are in cycle units. i.MX25 Applications Processor for Automotive Products, Rev Table 56. NOTE Freescale Semiconductor ...
Page 79
... Flags out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor ...
Page 80
... Figure 52 shows the ESAI HCKT timing diagram. HCKT SCKT (output) i.MX25 Applications Processor for Automotive Products, Rev first bit Figure 51. ESAI Receive Timing Diagram 95 96 Figure 52. ESAI HCKT Timing 70 72 last bit 75 77 Freescale Semiconductor ...
Page 81
... For internal clock For external clock 64 Clock low period For internal clock For external clock i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 95 97 Figure 53. ESAI HCKR Timing Table 60. Table 58. ESAI Timing Conditions In the i.MX25, the internal clock frequency is equal to the IP bus frequency ...
Page 82
... Freescale Semiconductor ...
Page 83
... FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card clock can reach 25 MHz • HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can reach 50 MHz i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 3 Symbol Expression — — ...
Page 84
... Figure 54. eSDHCv2 Timing Symbols TLH t THL ISU t IH SD1 Min. Max. Unit 1 0 400 2 0 25/50 MHz 3 0 20/52 MHz 100 400 6.5 — 6.5 — — 3 — 3 –3 3 2.5 — 4 2.5 — Freescale Semiconductor kHz kHz ...
Page 85
... FEC_RX_CLK pulse width high M4 FEC_RX_CLK pulse width low 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 62 describes the timing parameters (M1–M4) shown Table 62. MII Receive Signal Timing ...
Page 86
... Applications Processor for Automotive Products, Rev Table 63 describes the timing parameters (M5–M8) shown Table 63. MII Transmit Signal Timing 1 Characteristic Table 64 describes the timing parameter (M9) shown Min. Max. Unit 5 — ns — 35% 65% FEC_TX_CLK period 35% 65% FEC_TX_CLK period Freescale Semiconductor ...
Page 87
... FEC_MDIO (input) to FEC_MDC rising edge setup M13 FEC_MDIO (input) to FEC_MDC rising edge hold M14 FEC_MDC pulse width high M15 FEC_MDC pulse width low i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Min. 1.5 Table 65 describes the timing parameters (M10—M15) M14 M15 M10 ...
Page 88
... Applications Processor for Automotive Products, Rev Table 66 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Table 66. RMII Signal Timing Characteristic M17 Min. Max. Unit 35% 65% REF_CLK period 35% 65% REF_CLK period 3 — ns — — — ns Freescale Semiconductor ...
Page 89
... Vcc = +3.3 V ± 5% Figure 60 through Figure 63 show the FlexCAN timing, including timing of the standby and shutdown signals. TXD t ONTXD V DIFF RXD i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 67. Tx Pin Characteristics Symbol Min. Typ. 2 — — 0.8 OL Table 68. Rx Pin Characteristics Symbol Min ...
Page 90
... Because integer multiples are not possible, taking into account the range of frequencies at which the SoC has to operate, DPLLs work in FOL mode only. i.MX25 Applications Processor for Automotive Products, Rev 0.75 CC Bus Externally Driven 1.1V t SBRXDL t DRXDL OFFSHDN ONSHDN Bus Externally 0.5V Driven SHDNSB 0. Freescale Semiconductor ...
Page 91
... Bus free time between a STOP and START condition IC10 Rise time of both I2DAT and I2CLK signals IC11 Fall time of both I2DAT and I2CLK signals IC12 Capacitive load for each bus line (C i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 2 C) Timing 2 C module. Table 69 and Table 70 ...
Page 92
... The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal i.MX25 Applications Processor for Automotive Products, Rev Parameter ) b Standard Mode Unit Min. Max 4 4 3. 250 - ns 4 1000 ns - 300 ns - 400 pF Freescale Semiconductor ...
Page 93
... LD setup time T4 LD hold time T5 Wait between HSYNC and VSYNC rising edge T6 Wait between last data and HSYNC rising edge pixel clock period i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor T4 Description Table 71 Line n Line 1 T6 Min. Max. 22.5 1000 1 — ...
Page 94
... Applications Processor for Automotive Products, Rev Figure 66. LCDC TFT Mode Timing Diagram Description Table 73 lists the PWM timing characteristics. Line n Line 1 T6 Min. Ma Unit 22.5 1000 ns 1 — — — — — T Freescale Semiconductor ...
Page 95
... SIM card responds with Answer to Reset. Although the SIM interface has no defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816). i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Figure 67 ...
Page 96
... Applications Processor for Automotive Products, Rev /SI1 SI3 SI4 SI5 SI6 Figure 68. SIM Clock Timing Diagram Symbol trans 4 Tr/Tf 5 Tr/Tf SI2 SI4 SI5 SI6 Min. Max. 0.01 25 freq — 0.09 (1/S ) rise freq — 0.09 (1/S ) fall freq 10 25 — 1 — 1 Freescale Semiconductor Unit MHz ...
Page 97
... SIMx_RSTy is asserted (at time T1) • SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor RESPONSE Min. Max. — 200 ...
Page 98
... SIM card removal detection may be launched by the processor. i.MX25 Applications Processor for Automotive Products, Rev Min. Max. — 200 400 40,000 40,000 — RESPONSE 2 3 Unit clk cycles clk cycles clk cycles Table 77 shows the timing Freescale Semiconductor ...
Page 99
... Figure 75 show respectively the test clock input, boundary scan, test access port, and TRST timings for the SJC. Table 78 figures. TCK (Input) VIH SJ3 i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor SI7 SI8 SI9 SYMBOL S rst2clk S rst2dat S rst2ven ...
Page 100
... Figure 74. Test Access Port Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 9 100 SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid VIH SJ5 VIH SJ9 Freescale Semiconductor ...
Page 101
... In cases where SDMA TAP is put in the chain, the maximum TCK frequency is limited by the maximum ratio of 1:8 of SDMA core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock. 2 mid point voltage V M – i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor SJ13 Figure 75. TRST Timing Diagram Table 78. SJC Timing Parameters ...
Page 102
... MSB trss RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 0, CSPOL = 1) Table 79 tcsh tcl tch tdh trsh LSB tcsh tcl tch trsh tdh LSB tcsh tcl tch tdh trsh LSB tcsh tcl tch tdh trsh LSB Freescale Semiconductor and ...
Page 103
... Register select hold time rsh LCD_CLK LCD_RS LCD_CS LCD_DATA[15:0] LCD_CLK LCD_RS LCD_CS LCD_DATA[15:0] Figure 77. SLCDC Timing Diagram—Parallel Transfers to LCD Device i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Min cyc prop ( cyc prop prop prop ...
Page 104
... SS1 SS5 SS4 SS8 SS6 SS10 SS16 SS43 SS42 Typ. Max. — 4923 — — — — — — — — Table 81 describes the timing SS3 SS12 SS14 SS15 SS18 SS17 SS19 Freescale Semiconductor Units ns — — — — ...
Page 105
... SSI. • For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation). i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Parameter Internal Clock Operation Synchronous Internal Clock Operation Min ...
Page 106
... SS51 SS47 SS50 Parameter Internal Clock Operation Oversampling Clock Operation Table 82 describes the timing SS3 SS13 SS21 SS49 Min. Max. 81.4 — 36.0 — — 6.0 36.0 — — 6.0 — 15.0 — 15.0 — 15.0 — 15.0 10.0 — 0.0 — 15.04 — Freescale Semiconductor Unit ...
Page 107
... AUDn_TXFS (bl) (Input) AUDn_TXFS (wl) (Input) AUDn_TXD (Output) AUDn_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 80. SSI Transmitter with External Clock Timing Diagram i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Parameter SS22 SS25 SS26 SS27 SS31 SS37 SS44 Min. Max. ...
Page 108
... For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation). i.MX25 Applications Processor for Automotive Products, Rev. 9 108 Parameter External Clock Operation Synchronous External Clock Operation Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 109
... If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. • All timings are on pads when SSI is being used for data transfer. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor SS22 SS26 SS25 ...
Page 110
... With a 250 pF load Power Supply Requirements — Min. Typ. Max. Unit — 2 — bits — 1.6 — k — — 125 kHz — — 1.75 MHz 8 — 12.5 clk cycles 14 clk cycles 0 — — 2.1 mA 0.5 mA Freescale Semiconductor ...
Page 111
... ADC. After a conversion cycle eoc is asserted, a new conversion begins only when the i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Conditions — Touchscreen Interface — ...
Page 112
... Applications Processor for Automotive Products, Rev. 9 112 Figure 82. Start-up Sequence st ). The best way to guarantee this is to make the input multiplexer th ) Freescale Semiconductor ...
Page 113
... ADC operation, including the idle cycles. If the conditions are not met power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 113 ...
Page 114
... ADC with idle cycles between conversions. This diagram is valid for any value of N equal or greater than 1. Figure 84. ADC Usage with Idle Cycles Between Conversions 3.7.19 UART Timing This section describes the timing of the UART module in serial and parallel mode. i.MX25 Applications Processor for Automotive Products, Rev. 9 114 Freescale Semiconductor ...
Page 115
... Receive bit time 1 The UART receiver can tolerate 1/(16 exceed 3/( baud_rate Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16. baud_rate i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Symbol Min 1/F – ...
Page 116
... Bit 5 Bit 6 Bit 7 Parity Bit Max baud_rate ref_clk ) – T (3/16) (1 ref_clk baud_rate ref_clk UA6 UA5 Possible Bit 5 Bit 6 Bit 7 Parity Bit Max. ) 1/F + 1/(16 F baud_rate baud_rate baud_rate (5/16) (1/F ) baud_rate Freescale Semiconductor UA3 STOP BIT Units — — UA5 STOP BIT Units ) — — ...
Page 117
... Transmit USB_DAT_VP USB_SE0_VM Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high ...
Page 118
... Buffered data on DP when USB_TXOE_B is high In Buffered data on DM when USB_TXOE_B is high In Differential Rx data when USB_TXOE_B is high US6 Conditions/ Max. Unit Reference Signal — 5.0 ns — 5.0 ns — 5.0 ns 51.0 % — 8.0 ns USB_TXOE_B — 10.0 ns USB_TXOE_B — 3.0 ns — 3.0 ns Signal Description Freescale Semiconductor — ...
Page 119
... US12 Tx duty cycle US13 Enable Delay US14 Disable Delay US15 Rx rise/fall time US16 Rx rise/fall time US17 Rx rise/fall time i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor US9 US12 US17 Signal Signal Name Min. Source USB_DAT_VP Out — USB_SE0_VM Out — ...
Page 120
... Out (Tx) • data when USB_TXOE_B is low In (Rx) • data when USB_TXOE_B is high Out (Tx) • data when USB_TXOE_B low In (Rx) • data when USB_TXOE_B high In • Differential Rx data US4 US2 US5 Signal Description US1 US3 US6 Freescale Semiconductor ...
Page 121
... USB in VP_VM unidirectional mode. Table 96. Signal Definitions for USB VP_VM Unidirectional Mode Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Signal Name Direction Min. USB_DAT_VP Out USB_SE0_VM Out USB_TXOE_B Out ...
Page 122
... USB receive waveform in VP_VM unidirectional mode diagram. Receive USB_TXOE_B USB_VP1 US36 USB_VM1 USB_RCV Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode i.MX25 Applications Processor for Automotive Products, Rev. 9 122 US30 US34 US38 US40 US39 US41 US32 US31 US37 Freescale Semiconductor ...
Page 123
... Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus USB_Nxt In Next—The PHY asserts this signal to throttle the data i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Signal Direction Min. USB_DAT_VP Out — ...
Page 124
... Parallelism measurement shall exclude any effect of mark on top surface of package. i.MX25 Applications Processor for Automotive Products, Rev. 9 124 Table 99 US16 US16 US17 US17 Min. Max. Unit 6.0 — ns 0.0 — ns — 9.0 ns describes the timing Conditions/Reference Signal Figure 98: Freescale Semiconductor ...
Page 125
... Table 100 Package Ground, Power Sense, and Reference Contact Assignments Contact Name BATT_VDD P10 FUSE_VDD T17 MPLL_GND U17 MPLL_VDD U18 NGND_ADC Y13 NVCC_ADC W13 NVCC_CRM N14 NVCC_CSI J13, J14 i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 17 17 i.MX25 Production Package zzxz Contact Assignment 125 ...
Page 126
... USBPHY1_UPLLVSS N17 USBPHY1_VDDA K16 USBPHY1_VDDA_BIAS K19 USBPHY1_VSSA L19 USBPHY1_VSSA_BIAS J17 USBPHY2_VDD W18 USBPHY2_VSS W17 1 NVCC_DRYICE is a supply output. An external capacitor no less than 4 µF must be connected to it. A 4.7 µF capacitor is recommended. i.MX25 Applications Processor for Automotive Products, Rev. 9 126 Contact Assignment Freescale Semiconductor ...
Page 127
... A20 B6 A21 C7 A22 A5 A23 A6 A24 B7 A25 A7 SD0 A12 SD1 C13 SD2 B13 i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Power Rail I/O Buffer Type EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR EMI2 DDR ...
Page 128
... Keeper OUTPUT Low OUTPUT Low OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT Low OUTPUT High INPUT Keeper INPUT Keeper OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High OUTPUT High Freescale Semiconductor ...
Page 129
... LD0 Y7 2 LD1 V8 i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Power Rail I/O Buffer Type EMI2 DDR EMI1 GPIO EMI1 GPIO NFC GPIO EMI1 GPIO EMI1 DDR EMI1 DDR EMI1 DDR NFC GPIO ...
Page 130
... OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low OUTPUT Low INPUT 100 K Pull-Down INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper INPUT Keeper OUTPUT Low INPUT Keeper INPUT Keeper INPUT Keeper Freescale Semiconductor ...
Page 131
... KPP_ROW0 N4 KPP_ROW1 R1 KPP_ROW2 P3 KPP_ROW3 P2 KPP_COL0 P1 KPP_COL1 N3 KPP_COL2 N2 KPP_COL3 N1 FEC_MDC L1 FEC_MDIO L2 i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Power Rail I/O Buffer Type CSI GPIO CSI GPIO MISC GPIO MISC GPIO MISC GPIO MISC GPIO MISC GPIO MISC GPIO MISC GPIO ...
Page 132
... INPUT 47 K Pull-Up INPUT 47 K Pull-Up INPUT - INPUT 47 K Pull-Up INPUT 47 K Pull-Up INPUT 100 K Pull-Up ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - ANALOG - INPUT - INPUT 100 K Pull-Down INPUT 100 K Pull-Down INPUT - INPUT 100 K Pull-Up INPUT - INPUT - INPUT - OUTPUT Low Freescale Semiconductor ...
Page 133
... The state immediately after reset and before ROM firmware or software has executed. 2 During power-on reset this port acts as input for fuse override signal. 3 During power-on reset this port acts as output for diagnostic signal. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Power Rail I/O Buffer Type CRM GPIO CRM ...
Page 134
... NC_BGA_B20 NC_BGA_E17 NC_BGA_H17 NC_BGA_J19 NC_BGA_M18 NC_BGA_P20 NC_BGA_U15 NC_BGA_U16 NC_BGA_V15 NC_BGA_V16 NC_BGA_V17 NC_BGA_W14 NC_BGA_Y2 NC_BGA_Y14 NC_BGA_Y17 i.MX25 Applications Processor for Automotive Products, Rev. 9 134 Contact Assignment B20 E17 H17 J19 M18 P20 U15 U16 V15 V16 V17 W14 Y2 Y14 Y17 Freescale Semiconductor ...
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... Package Ball Map Table 103 shows the i.MX25 17 17 package ball map. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 103. i.MX25 17 17 Package Ball Map 135 ...
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... Table 103. i.MX25 17 17 Package Ball Map (continued) i.MX25 Applications Processor for Automotive Products, Rev. 9 136 Freescale Semiconductor ...
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... Table 103. i.MX25 17 17 Package Ball Map (continued) i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor 137 ...
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... Min and for NVCC_DRYICE signal. 13. 13. 36, the frequency specification has been updated 37, the frequency 127. to include new row for WE19. to include Min and Max values of FUSE_VDD. Freescale Semiconductor 76: ...
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... Updated values in • Updated Table Rev. 0 6/2009 Initial release. i.MX25 Applications Processor for Automotive Products, Rev. 9 Freescale Semiconductor Table 104. Revision History (continued) Substantive Change(s) 1, “Ordering Information,” to include new part numbers. “i.MX25 Parts Functional Differences.” to include new part numbers. ...
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... Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...