71V424L10YG IDT, 71V424L10YG Datasheet - Page 7

• Manufacturer Part Number: 71V424L10YG
• Description: SRAM 512Kx8 ASYNCHRONOUS 3.3V CMOS SRAM
• Manufacturer: IDT

Specifications of 71V424L10YG

• Rohs: yes
• Part # Aliases: IDT71V424L10YG

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the t
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
IDT71V424S/YS, IDT71V424L/YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
ADDRESS
ADDRESS
data to be placed on the bus for the required t
is the specified t
write period.
DATA
DATA
DATA
OUT
WE
WE
CS
CS
IN
IN
WP
.
t
AS
t
AS
(3)
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
t
WHZ
(5)
t
AW
t
AW
t
t
WC
WP
6.42
WP
t
t
CW
WC
7
(2)
must be greater than or equal to t
HIGH IMPEDANCE
t
DATA
DW
t
DW
DATA
IN
Commercial and Industrial Temperature Ranges
VALID
IN
VALID
t
DH
t
t
WR
OW
WHZ
t
WR
(5)
+ t
t
DH
DW
to allow the I/O drivers to turn off and
(1, 4)
(3)
(1, 2, 4)
t
CHZ
3622 drw 08
(5)
3622 drw 09
CW