MAX6745XKVD3+T Maxim Integrated, MAX6745XKVD3+T Datasheet
MAX6745XKVD3+T
Specifications of MAX6745XKVD3+T
Related parts for MAX6745XKVD3+T
MAX6745XKVD3+T Summary of contents
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... Exposed pad. MAXQ is a registered trademark of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata. ...
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... In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 In-Circuit Debug and JTAG Interface Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Applications Information Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Deviations from the MAXQ610 User’s Guide for the MAXQ613 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Development and Technical Support Package Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2 TABLE OF CONTENTS Maxim Integrated ...
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... Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1: Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Maxim Integrated LIST OF FIGURES LIST OF TABLES MAXQ613 3 ...
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... PFM_ON t (Note 8) PFW MIN TYP MAX V 3.6 RST 1.62 1.8 1.98 1.75 1.8 1.85 1.64 1.67 1.70 1 1.42 1.0 3.25 4 0.2 2.0 0 29.5 27 ((PCI - ))]/PCI NANO 100 375 + (8192 x t HFXIN) 150 GND DD 0 Maxim Integrated UNITS ...
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... EXTERNAL CLOCK INPUT External Clock Frequency External Clock Period External Clock Duty Cycle t XCLK_DUTY System Clock Frequency System Clock Period NANOPOWER RING Nanopower Ring Frequency Nanopower Ring Duty Cycle Nanopower Ring Current Maxim Integrated CONDITIONS 3.3V +25NC IHYS DD A IL_HFXIN IH_HFXIN t ...
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... CK MIN TYP MAX 8.3 23 MCK t SPI_RF MCK t SPI_RF MCK t SPI_RF MCK t SPI_RF t /2 SCK t SPI_RF t SPI_RF Maxim Integrated UNITS s MHz ms Fs Cycles Years Hz UNITS MHz MHz ...
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... Note 9: The maximum total current, I maximum specified voltage drop. This does not include the IRTX output. Note 10: Programming time does not include overhead associated with utility ROM interface. Note 11: AC electrical specifications are guaranteed by design and are not production tested. Maxim Integrated CONDITIONS t SIH ...
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... No devices other than the capacitor should be connected to this pin. Pin Configurations 34 35 N. MAXQ613 TQFN (7mm × 7mm) Pin Description FUNCTION 22 P1.5/INT5 21 P1.4/INT4 20 GND REGOUT 17 GND 16 N.C. 15 N.C. 14 P1.3/INT3 13 P1.2/INT2 EP 12 P1.1/INT1 Maxim Integrated ...
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... Maxim Integrated NAME RESET PIN Digital, Active-Low, Reset Input/Output. The device remains in reset as long as this pin is low and begins executing from the utility ROM at address 8000h when this pin returns to a high state. The pin includes pullup current source; if this pin is driven by an external device, it should RESET be driven by an open-drain source capable of sinking in excess of 4mA ...
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... EXTERNAL INTERRUPT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 SPECIAL FUNCTION P2.0 SPI: Master Out-Slave In P2.1 SPI: Master In-Slave Out P2.2 SPI: Slave Clock P2.3 SPI: Active-Low Slave Select P2.4 JTAG: Test Clock P2.5 JTAG: Test Data In P2.6 JTAG: Test Mode Select P2.7 JTAG: Test Data Out INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Maxim Integrated ...
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... Operating from DC to 12MHz, almost all instructions exe- cute in a single clock cycle (83.3ns at 12MHz), enabling nearly 12MIPS true-code operation. When active device operation is not required, an ultra-low-power stop mode Maxim Integrated Block Diagram can be invoked from software, resulting in quiescent current consumption of less than 0.2FA (typ) and 2.0FA (max) ...
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... MAXQ610 User’s Guide) MAXIMUM PRIVILEGE LEVEL Medium Utility ROM High Low High Low Maxim Integrated ...
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... All watchdog timer resets follow the pro- grammed interrupt timeouts by 512 system clock cycles. If the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. See Table 2. Maxim Integrated WATCHDOG INTERRUPT TIMEOUT 2.7ms 21.9ms 174.7ms 1 ...
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... IRCLK resolution. The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin. If IRTXPOL = 1, the IRCA = 0002h IRMT = 5 IRCA, IRMT, IRDATA SAMPLED AT END OF IRV DOWN-COUNT INTERVAL Transmission Maxim Integrated ...
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... IRTX IRTXPOL = 1 IRTX IRTXPOL = 0 Figure 3. IR Transmission Waveform (IRCFME = 0) Maxim Integrated condition, as defined by IRTXPOL, is output on the IRTX pin during the next IRMT cycles. The IR timer acts as a down counter in transmit mode transmission starts when the IREN bit is set to 1 when IRMODE = 1 ...
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... Resets IRV content to 0000h (if IRXRL = 1). 4) Continues counting again until the next qualified event. If the IR timer value rolls over from 0FFFFh to 0000h before a qualified event happens, the IR timer overflow (IROV) flag is set to 1 and an interrupt is generated Receive IRMT IRMT Maxim Integrated ...
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... IRV register is counting system IRCLK clocks or IRCA-defined carrier cycles. The IRXRL bit defines whether the IRV register is reloaded with 0000h on detection of a qualified edge (per the IRXSEL[1:0] bits). Figure 6 and the descriptive sequence embedded Maxim Integrated CARRIER MODULATION 0 IRCAL + 1 1 ...
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... Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of an active SSEL state (active low or active high) through the slave active select. IRMT = PULSE COUNTING 8 9 DATA BITS STOP BITS 8 N Maxim Integrated ...
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... CKPOL/CKPHA 0/1 OR 1/0 SCLK CKPOL/CKPHA 0/0 OR 1/1 MOSI MISO Figure 7. SPI Master Communication Timing SHIFT SSEL t SSE SCLK CKPOL/CKPHA 0/1 OR 1/0 SCLK CKPOL/CKPHA 0/0 OR 1/1 MOSI MISO Figure 8. SPI Slave Communication Timing Maxim Integrated SAMPLE SHIFT SAMPLE t MCK t t MCH MCL t MOH t MOV MSB MSB MIS MIH MSB ...
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... ROM utility functions provided for in-application flash memory programming: /* Write one 16-bit word to code address ‘dest’. * Dest must be aligned to 16 bits. = 1MI Q50 Returns 0 = failure OK. */ int flash_write (uint16_t dest, uint16_t data); ROM Loader Loading Flash Memory Maxim Integrated ...
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... Background mode: CPU is executing the normal user program Allows the host to configure and set up the in-circuit debugger Maxim Integrated • Debug mode: Debugger takes over the control of the CPU Read/write accesses to internal registers and memory Single-step of the CPU for trace operation The interface to the debug engine is the TAP control- ler ...
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... CPU reset. In these cases, the CPU exits the reset state in less than 20 crystal cycles after the reset source is removed. t < t PFW t ≥ ≥ t PFW monitored for an additional nanopower DD remains above ≥ t PFW PFW > V during RST for RST I Maxim Integrated ...
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... Table 4. Power-Fail Detection States During Normal Operation INTERNAL STATE POWER-FAIL REGULATOR (Periodically (Periodically) I Off Maxim Integrated CRYSTAL SRAM OSCILLATOR RETENTION Off Off Off Off On On Off Off Off Off MAXQ613 COMMENTS — ...
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... Exit stop mode. Application enters stop mode. Yes V > RST CPU in stop mode. V < V < POR DD RST Power-fail detected. Yes CPU goes into reset. Power-fail monitor turns on periodically. V < POR — Device held in reset. No operation allowed XTAL_RDY Maxim Integrated ...
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... HIGH) INTERRUPT Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled INTERNAL STATE POWER-FAIL REGULATOR A Off B Off C On Maxim Integrated B C CRYSTAL OSCILLATOR RETENTION Off Off Off Off On On MAXQ613 D ...
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... RST An interrupt occurs that causes the CPU to exit stop mode. Yes Power-fail monitor is turned on, detects a power-fail, and puts CPU in reset. Power-fail monitor is turned on periodically. V < POR — Device held in reset. No operation allowed. Additional Documentation MAXQ613 revision-specific errata sheet Maxim Integrated ...
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... Port 3 Input Register (PI3) • Port 4 Output Register (PO4) • Port 4 Direction Register (PD4) • Port 4 Input Register (PI4) Maxim Integrated for the MAXQ613 Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: • ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...