CAT1641WI-25-G ON Semiconductor, CAT1641WI-25-G Datasheet - Page 7

• Manufacturer Part Number: CAT1641WI-25-G
• Description: Supervisory Circuits CPU w/64K
• Manufacturer: ON Semiconductor

Specifications of CAT1641WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active High, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 3 V

Reset Controller Description
correct system operation during brownout and power
up/down conditions. They are configured with opendrain
RESET/RESET outputs.
active until V
driving the outputs for approximately 200 ms (t
reaching V
will cease to drive the reset output. At this point the reset
output will be pulled up or down by their respective pull
up/down resistors.
active when V
output will be valid so long as V
device is designed to ignore the fast negative going V
transient pulses (glitches).
Manual Reset Operation
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
RESET
RESET
The CAT1640/41 precision Reset controllers ensure
During power−up, the RESET/RESET output remains
During power−down, the RESET/RESET outputs will be
Reset output timing is shown in Figure 1.
The RESET pin can operate as reset output and manual
V
CC
V
RVALID
V
TH
TH
CC
. After the t
CC
reaches the V
falls below V
PURST
TH
CC
timeout interval, the device
threshold and will continue
t
TH
is > 1.0 V (V
PURST
. The RESET/RESET
Figure 1. RESET/RESET Output Timing
RVALID
PURST
DEVICE OPERATON
http://onsemi.com
) after
). The
CC
t
GLITCH
7
t
RPD
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
generate a reset pulse.
Hardware Data Protection
of the data corruption issues that have long been associated
with serial EEPROMs. Data corruption occurs when
incorrect data is stored in a memory location which is
assumed to hold correct data.
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output is active, in
progress communications to the EEPROM are aborted and
no new communications are allowed. In this condition an
internal write cycle to the memory can not be started, but an
in progress internal non−volatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5 ms) before VCC reaches the minimum value
of 2 V.
When RESET I/O is driven to the active state, the 200 ms
Glitches shorter than 100 ns on RESET input will not
The CAT1640/41 family has been designed to solve many
Whenever the device is in a Reset condition, the
t
PURST
t
RPD