CAT1641WI-25-G ON Semiconductor, CAT1641WI-25-G Datasheet - Page 9

• Manufacturer Part Number: CAT1641WI-25-G
• Description: Supervisory Circuits CPU w/64K
• Manufacturer: ON Semiconductor

Specifications of CAT1641WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active High, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 3 V

serial EEPROM that supports the I
protocol. This Inter−Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter and
any device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
Both the Master device and Slave device can operate as
either transmitter or receiver, but the Master device controls
which mode is activated.
I
follows:
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant bits
of the 8−bit slave address are programmable in metal and the
default is 1010.
or Write operation is to be performed. When this bit is set to
1, a Read operation is selected, and when set to 0, a Write
operation is selected.
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
2
C Bus Protocol
The CAT1640 and CAT1641 feature a 64 kbit embedded
The features of the I
The Master begins a transmission by sending a START
The last bit of the slave address specifies whether a Read
After a successful data transfer, each receiving device is
The CAT1640/41 responds with an acknowledge after
1. Data transfer may be initiated only when the bus is
not busy.
SCL
SDA
2
C bus protocol are defined as
8TH BIT
BYTE n
2
C Bus data transmission
EMBEDDED EEPROM OPERATON
ACK
Figure 4. Write Cycle Timing
DEVICE ADDRESSING
ACKNOWLEDGE
http://onsemi.com
STOP
CONDITION
9
Start Condition
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT1640/41 monitors the SDA
and SCL lines and will not respond until this condition is
met.
Stop Condition
determines the STOP condition. All operations must end
with a STOP condition.
address byte, the CAT1640/41 monitors the bus and
responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT1640/41 then perform a Read or Write operation
depending on the R/W bit.
8 bits of data, releases the SDA line and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT1640/41 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
After the Master sends a START condition and the slave
When the CAT1640/41 begins a READ mode it transmits
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
t WR
START
CONDITION
ADDRESS