IS62C256AL-45ULI ISSI, Integrated Silicon Solution Inc, IS62C256AL-45ULI Datasheet - Page 7

• Manufacturer Part Number: IS62C256AL-45ULI
• Description: IC SRAM 256KBIT 45NS 28SOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Asynchronousr

Specifications of IS62C256AL-45ULI

• Memory Size: 256K (32K x 8)
• Package / Case: 28-SOP
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 45ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 25 mA
• Organization: 32 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Density: 256Kb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 15b
• Package Type: SOP
• Operating Temp Range: -40C to 85C
• Supply Current: 25mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 8b
• Number Of Words: 32K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1043

IS65C256AL
IS62C256AL
AC WAVEFORMS
WRITE CYCLE NO. 1
Integrated Silicon Solution, Inc.
Rev. C
07/12/07
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
4. Tested with OE HIGH.
Symbol
t
t
t
t
t
t
t
t
t
output loading specified in Figure 1.
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
WC
SCS
AW
HA
SA
PWE
PWE
SD
HD
1,
2
ADDRESS
(4)
D
OUT
WE
D
CE
IN
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
(CE Controlled, OE is HIGH or LOW)
DATA UNDEFINED
t
SA
t
HZWE
t
VALID ADDRESS
AW
t
t
PWE1
PWE2
t
t
SCS
WC
Min.
(1,3)
25
15
15
15
12
0
0
0
HIGH-Z
(1 )
-25 ns
(Over Operating Range)
t
Max.
SD
DATA
—
—
—
—
—
—
—
—
IN
VALID
t
Min. Max.
HD
t
45
35
25
25
20
0
0
0
-45 ns
LZWE
t
HA
—
—
—
—
—
—
—
—
CS_WR1.eps
Unit
ns
ns
ns
ns
ns
ns
ns
ns
7