IS61WV5128BLL-10TLI ISSI, Integrated Silicon Solution Inc, IS61WV5128BLL-10TLI Datasheet - Page 13

• Manufacturer Part Number: IS61WV5128BLL-10TLI
• Description: IC SRAM 4MBIT 10NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Asynchronousr

Specifications of IS61WV5128BLL-10TLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (512K x 8)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Access Time: 10 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.4 V
• Maximum Operating Current: 40 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 40mA
• Operating Supply Voltage (min): 2.4V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1108; IS61WV5128BLL-10TLI; Q4714568

IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
Symbol
t
t
t
t
t
t
t
t
t
t
t
wC
sCe
Aw
hA
sA
Pwe
Pwe
sd
hd
hzwe
lzwe
levels of 0.4V to V
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
1
2
(3)
(3)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
dd
-0.3V and output loading specified in Figure 1a.
Min.
20
12
12
12
17
—
0
0
9
0
3
-20 ns
Max.
—
—
—
—
—
—
—
—
—
—
9
(1,2)
(Over Operating Range)
Min.
25
18
15
18
20
12
—
0
0
0
5
-25 ns
Max.
12
—
—
—
—
—
—
—
—
—
—
Min.
35
25
25
30
30
15
—
0
0
0
5
-35 ns
Max.
—
—
—
—
—
—
—
—
—
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13