IS42S32400D-7TL ISSI, Integrated Silicon Solution Inc, IS42S32400D-7TL Datasheet - Page 44
![IC SDRAM 128MBIT 143MHZ 86TSOP](/photos/7/23/72320/is42s32400d-7tl_sml.jpg)
IS42S32400D-7TL
Manufacturer Part Number
IS42S32400D-7TL
Description
IC SDRAM 128MBIT 143MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S32400D-7TL.pdf
(60 pages)
Specifications of IS42S32400D-7TL
Package / Case
86-TSOPII
Memory Size
128M (4Mx32)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
32 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1023
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
26
Part Number:
IS42S32400D-7TL
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS42S32400D-7TLI-TR
Manufacturer:
ISSI
Quantity:
1 000
IS42S32400D
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
44
COMMAND
INTERNAL
ADDRESS
CLOCK
INTERNAL
COMMAND
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
n
T2
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH; the
internal clock and related operation will resume on the
subsequent positive clock edge.
T3
D
Integrated Silicon Solution, Inc. — www.issi.com
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
D
T5
OUT
D
DON'T CARE
n+2
NOP
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
03/03/09
Rev. F