IS62LV256-70U-TR ISSI, IS62LV256-70U-TR Datasheet - Page 8
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IS62LV256-70U-TR
Manufacturer Part Number
IS62LV256-70U-TR
Description
SRAM 256K 32Kx8 70ns 3.3v
Manufacturer
ISSI
Type
Asynchronousr
Datasheet
1.IS62LV256-70TI-TR.pdf
(13 pages)
Specifications of IS62LV256-70U-TR
Product Category
SRAM
Memory Size
256 Kbit
Organization
32 K x 8
Access Time
70 ns
Supply Voltage - Max
3.465 V
Supply Voltage - Min
3.135 V
Maximum Operating Current
20 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
SOP-28
Interface
TTL
Factory Pack Quantity
1000
IS65LV256AL
IS62LV256AL
WRITE CYCLE NO. 2 (CE Controlled)
8
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
OUT
WE
D
CE
IN
DATA UNDEFINED
t
SA
≥
V
Ih
.
(1,2)
Integrated Silicon Solution, Inc. — www.issi.com —
t
HZWE
t
AW
t
t
SCE
PWE
t
WC
HIGH-Z
t
SD
DATA-IN VALID
t
HA
t
t
HD
LZWE
1-800-379-4774
05/09/12
Rev. C