C8051F717-GMR Silicon Labs, C8051F717-GMR Datasheet - Page 192

• Manufacturer Part Number: C8051F717-GMR
• Description: 8-bit Microcontrollers - MCU 16kB ADC Cap Sense
• Manufacturer: Silicon Labs

Specifications of C8051F717-GMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051F70x/71x
28.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Definition 28.3. P0MASK: Port 0 Mask Register
SFR Address = 0xF4; SFR Page = 0
192
Name
Reset
7:0
Bit
Type
Bit
P0MASK[7:0]
Name
7
0
Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
6
0
5
0
Rev. 1.0
4
P0MASK[7:0]
0
R/W
Function
3
0
2
0
1
0
0
0