C8051F545-IQR Silicon Labs, C8051F545-IQR Datasheet - Page 63

• Manufacturer Part Number: C8051F545-IQR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 8 kB 1 kB SPI UART I2C
• Manufacturer: Silicon Labs

Specifications of C8051F545-IQR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

8. Comparators
The C8051F54x devices include two on-chip programmable voltage Comparators. A block diagram of the
comparators is shown in Figure 8.1, where “n” is the comparator number (0 or 1). The two Comparators
operate identically except that Comparator0 can also be used a reset source. For input selection details,
refer to SFR Definition 8.5 and SFR Definition 8.6.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “18.4. Port I/O Initialization” on page 152). Comparator0 may also be used as a
reset source (see Section “16.5. Comparator0 Reset” on page 133).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.5). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 8.6). The CMX1P1-
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “18.1. Port I/O Modes of Operation” on page 148).
Comparator
Input Mux
CPTnMD
Figure 8.1. Comparator Functional Block Diagram
CPn +
CPn -
+
-
CPTnCN
GND
VIO
CPnRIF
CPnFIF
Decision
Reset
Tree
Rev. 1.1
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CPnEN
Crossbar
0
1
EA
C8051F54x
0
1
CPnA
Interrupt
CPn
CPn
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