MAX6708YKA+T Maxim Integrated, MAX6708YKA+T Datasheet - Page 11

• Manufacturer Part Number: MAX6708YKA+T
• Description: Supervisory Circuits uP Supervisor
• Manufacturer: Maxim Integrated
• Series: MAX6701, MAX6701A, MAX6702, MAX6702A, MAX6703, MAX6703A, MAX6704, MAX6705, MAX6705A, MAX6706, MAX6706A, MAX6707, MAX6707A, MAX6708r

Specifications of MAX6708YKA+T

• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.5 V, 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.12 V
• Overvoltage Threshold: 2.25 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 300 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 714 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 6 uA
• Supply Voltage - Min: 1.2 V

Table 3. Channel Selection in Single-Ended Mode (SGL/
Table 4. Channel Selection in Differential Mode (SGL/
SEL2
SEL2
2) Use a general-purpose I/O line on the CPU to pull
3) Transmit TB1 and simultaneously receive a byte
4) Transmit a byte of all zeros ($00 HEX) and simulta-
5) Transmit a byte of all zeros ($00 HEX) and simulta-
6) Pull CS on the MAX186/MAX188 high.
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
CS on the MAX186/MAX188 low.
and call it RB1. Ignore RB1.
neously receive byte RB2.
neously receive byte RB3.
SEL1
SEL1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
______________________________________________________________________________________
SEL0
SEL0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CH0
CH0
+
+
–
CH1
CH1
+
+
–
CH2
+
CH2
+
–
DIFF
DIFF
CH3
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of dead time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
In unipolar input mode, the output is straight binary
(see Figure 15). For bipolar inputs, the output is
twos-complement (see Figure 16). Data is clocked out
at the falling edge of SCLK in MSB-first format.
Low-Power, 8-Channel,
+
= 0)
CH3
= 1)
+
–
CH4
Serial 12-Bit ADCs
+
CH4
+
–
CH5
+
CH5
+
–
CH6
+
CH6
+
–
CH7
Digital Output
+
CH7
AGND
+
–
–
–
–
–
–
–
–
–
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