MAX6708YKA+T Maxim Integrated, MAX6708YKA+T Datasheet - Page 5

• Manufacturer Part Number: MAX6708YKA+T
• Description: Supervisory Circuits uP Supervisor
• Manufacturer: Maxim Integrated
• Series: MAX6701, MAX6701A, MAX6702, MAX6702A, MAX6703, MAX6703A, MAX6704, MAX6705, MAX6705A, MAX6706, MAX6706A, MAX6707, MAX6707A, MAX6708r

Specifications of MAX6708YKA+T

• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.5 V, 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.12 V
• Overvoltage Threshold: 2.25 V
• Output Type: Active High, Active Low, Push-Pull
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 300 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Maximum Power Dissipation: 714 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 6 uA
• Supply Voltage - Min: 1.2 V

ELECTRICAL CHARACTERISTICS (continued)
(V
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)
Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4: Ground on-channel; sine wave applied to all off channels.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: Measured at V
Note 9: The common-mode range for the analog inputs is from V
TIMING CHARACTERISTICS
(V
Positive Supply Rejection
(Note 8)
Negative Supply Rejection
(Note 8)
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
(Note 6)
CS Rise to SSTRB Output Disable
(Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
DD
DD
= 5V ±5%; V
= 5V ±5%; V
been calibrated.
PARAMETER
PARAMETER
SS
SS
DD
=0V or -5V, T
_______________________________________________________________________________________
= 0V or -5V; f
= 5.0V; V
SUPPLY
+5% and V
SS
A
CLK
= 0V; unipolar input mode.
= T
SYMBOL
SYMBOL
t
MIN
SSTRB
PSR
PSR
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
t
t
t
t
t
t
t
t
t
t
t
t
CSS
CSH
t
SDV
SCK
STR
DH
DO
CH
AZ
DS
DV
TR
CL
SUPPLY
to T
MAX
V
full-scale input
V
full-scale input
C
C
C
C
External clock mode only, C
External clock mode only, C
Internal clock mode only
-5% only.
DD
SS
, unless otherwise noted.)
LOAD
LOAD
LOAD
LOAD
= -5V ±5%; external reference, 4.096V;
= 5V ±5%; external reference, 4.096V;
= 100pF
= 100pF
= 100pF
= 100pF
CONDITIONS
CONDITIONS
SS
to V
Low-Power, 8-Channel,
MAX18_ _C/E
MAX18_ _M
DD
.
LOAD
LOAD
= 100pF
= 100pF
Serial 12-Bit ADCs
100
100
200
200
1.5
MIN
20
20
MIN
0
0
A
= T
MIN
±0.06
±0.01
TYP
TYP
to T
MAX
MAX
±0.5
±0.5
MAX
150
200
100
100
200
200
200
, unless otherwise
0
UNITS
UNITS
mV
mV
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5