STM8L152M8T3 STMicroelectronics, STM8L152M8T3 Datasheet - Page 7

• Manufacturer Part Number: STM8L152M8T3
• Description: 8-bit Microcontrollers - MCU 8-bit Ultralow MCU LCD 80pin 64kb Flash
• Manufacturer: STMicroelectronics

Specifications of STM8L152M8T3

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: STM8
• Data Bus Width: 8 bit

STM8L15xx8, STM8L15xR6
List of figures
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Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
High density and medium+ density STM8L15xx device block diagram . . . . . . . . . . . . . . 13
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM8L151M8 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L152M8 80-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L151R8 and STM8L151R6 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . 26
STM8L152R8 and STM8L152R6 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8L151C8 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8L152C8 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical I
Typical I
Typical I
Typical I
Typical I
Typical IDD(AH) vs. V
Typical IDD(Halt) vs. V
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Typical HSI frequency vs. V
Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical pull-up resistance R
Typical pull-up current I
Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical NRST pull-up resistance R
Typical NRST pull-up current I
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SPI1 timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum dynamic current consumption on V
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Power supply and reference decoupling (V
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 117
80-pin low profile quad flat package (14 x 14 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical I
DD(RUN)
DD(Wait)
DD(Wait)
DD(LPR)
DD(LPW)
DD(RUN)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
from RAM vs. V
from Flash (HSI clock source), f
vs. V
from Flash vs. V
vs. V
from RAM vs. V
DD
DD
DD
DD
pu
(LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 79
(LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . 81
(LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
(internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 85
vs. V
DD
PU
Doc ID 17943 Rev 5
pu
vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DD
DD
vs. V
DD
DD
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PU
(HSI clock source), f
DD
(HSI clock source), f
(HSI clock source), f
vs. V
DD
with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
REF+
DD
REF+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
not connected to V
CPU
supply pin during ADC
= 16 MHz . . . . . . . . . . . . . . . . . . . . 77
CPU
CPU
CPU
= 16 MHz . . . . . . . . . . . . . . 77
= 16 MHz . . . . . . . . . . . . . 74
=16 MHz . . . . . . . . . . . . . . 74
DDA
). . . . . . . . . . . . . 117
List of figures
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