M93C66-WMN6P STMicroelectronics, M93C66-WMN6P Datasheet - Page 9

• Manufacturer Part Number: M93C66-WMN6P
• Description: IC EEPROM 4KBIT 2MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M93C66-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 512 x 8
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Configuration: 512 X 8, 256 X 16
• Clock Frequency: 2MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5672-5

Erase
The Erase Byte or Word (ERASE) instruction sets
the bits of the addressed memory byte (or word) to
1. Once the address has been correctly decoded,
the falling edge of the Chip Select Input (S) starts
the self-timed Erase cycle. The completion of the
cycle can be detected by monitoring the Ready/
Busy line, as described in the
TUS
Write
For the Write Data to Memory (WRITE) instruction,
8 or 16 data bits follow the op-code and address
bits. These form the byte or word that is to be writ-
ten. As with the other bits, Serial Data Input (D) is
sampled on the rising edge of Serial Clock (C).
Figure 5. ERASE, ERAL Sequences
Note: For the meanings of An and Xn, please see
section.
ERASE
ERASE
ALL
READY/BUSY STA-
S
Q
S
Q
D
D
Table
5.,
1 1
1
CODE
CODE
OP
OP
0
Table 6.
1
0
1
An
0
ADDR
ADDR
M93C86, M93C76, M93C66, M93C56, M93C46
Xn X0
and
A0
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed. The completion of the cycle can be
detected by monitoring the Ready/Busy line, as
described later in this document.
Once the Write cycle has been started, it is inter-
nally self-timed (the external clock signal on Serial
Clock (C) may be stopped or left running after the
start of a Write cycle). The cycle is automatically
preceded by an Erase cycle, so it is unnecessary
to execute an explicit erase instruction before a
Write Data to Memory (WRITE) instruction.
Table
7..
BUSY
BUSY
STATUS
STATUS
CHECK
CHECK
READY
READY
AI00879B
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