M24256-BWMN6TP STMicroelectronics, M24256-BWMN6TP Datasheet
M24256-BWMN6TP
Specifications of M24256-BWMN6TP
M24256-BWMN6TP
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M24256-BWMN6TP Summary of contents
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... More than 40-year data retention ■ Packages 2® – ECOPACK (RoHS compliant and halogen-free) December 2010 M24256-BF M24256-BR M24256-BW M24256-DR 256 Kbit serial I²C bus EEPROM with three Chip Enable lines 208 mils width 150 mils width TSSOP8 (DW) UFDFPN8 (MB) 2 × (MLP) Doc ID 6757 Rev 22 ...
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... Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 Page Write (memory array 3.9 Write Identification Page (M24256-D only 3.10 Lock Identification Page (M24256-D only 3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 3.13 Read operations ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.18 Reading the lock status (M24256-D only 3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Doc ID 6757 Rev 22 Contents 3/43 ...
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... List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device select code (for memory array Table 3. Device select code to access the Identification page (M24256-DR only Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections (top view, marking side, with balls on the underside Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Figure Fast mode (f C bus parasitic capacitance (C 2 Figure Fast mode Plus (f bus parasitic capacitance (C 2 Figure 7 ...
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... The M24256-Bx devices are I (EEPROM). They are organized × 8 bits. The M24256-DR also offers an additional page, named the Identification Page (64 bytes) which can be written and (later) permanently locked in Read-only mode. This Identification Page offers flexibility in the application board production line can be used to store unique identification parameters and/or parameters specific to the production line ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 2. Package connections 1. See Package mechanical data Figure 3. WLCSP connections (top view, marking side, with balls on the underside SCL SDA section for package dimensions, and how to identify pin- SDA V SCL SS Doc ID 6757 Rev 22 Description AI04035e ai14712 7/43 ...
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... Control (WC) is driven High. When unconnected, the signal is internally read as V Write operations are allowed. When Write Control (WC) is driven High, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR indicates how the value of the pull-up resistor can be calculated M24xxx ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 2.5 V ground the reference for the V SS 2.6 Supply voltage (V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V Table 10). In order to secure a stable DC supply voltage recommended to decouple the ...
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... Figure Fast mode Plus (f bus parasitic capacitance (C 100 Bus line capacitor (pF) 10/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR = 400 kHz): maximum bus When time constant must be below the 400 ns time constant line represented on the left 100 1000 Bus line capacitor (pF) ...
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... The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. Device select code to access the Identification page (M24256-DR only) Device select code 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. ...
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... Signal description Table 4. Most significant address byte b15 b14 Table 5. Least significant address byte b7 b6 12/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR b13 b12 b11 Doc ID 6757 Rev 22 b10 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 3 Device operation The device supports the I data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Serial Data (SDA) during the 9 the device select code, it deselects itself from the bus, and goes into Standby mode. Table 6. Operating modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write 14/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR (1) RW bit WC Bytes ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 8. Write mode sequences with (data write inhibited) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel Byte addr Byte addr R/W NO ACK NO ACK Data in N ...
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... NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. 16/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR , and the successful completion of a Write operation, W Figure 9. ...
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... It is therefore recommended to write data by word (4 bytes) at address 4*N (where integer) in order to benefit from the larger amount of Write cycles. The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-bytes. ...
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... Device operation Figure 9. Write mode sequences with (data write enabled) WC Byte Write WC Page Write WC (cont'd) Page Write (cont'd) 18/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR ACK ACK Dev sel Byte addr Byte addr R/W ACK ACK Dev sel Byte addr Byte addr R/W ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 10. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device 3.12 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (t ...
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... Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 20/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR ACK NO ACK Dev sel ...
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... Reading the Identification Page (M24256-D only) The Identification Page (64 bytes additional page which can be written and (later) permanently locked in Read-only mode. The Identification Page can be read by issuing a Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b ...
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... Device operation 3.18 Reading the lock status (M24256-D only) The locked/unlocked status of the Identification page can be checked by issuing a specific truncated command [Identification Page Write instruction + one data byte]: this data byte will be acknowledged if the Identification page is unlocked, while it will not be acknowledged if the Identification page is locked ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 4 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied ...
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... Table 11. AC test measurement conditions Symbol C Load capacitance bus SCL input rise/fall time SDA input fall time Input levels Input and output timing reference levels 24/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR Parameter Parameter Parameter Parameter Doc ID 6757 Rev 22 Min. Max. Unit 2.5 5.5 V – ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 12. AC test measurement I/O waveform Table 12. Input parameters Symbol C Input capacitance (SDA Input capacitance (other pins) IN Input impedance ( (E2, E1, E0, WC) Input impedance ( (E2, E1, E0, WC) 1. Sampled only, not 100% tested. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). ...
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... Output low voltage OL 1. Only for devices operating Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle t 26/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR Test conditions (see Table ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 15. DC characteristics (voltage range R) Symbol Parameter Input leakage current I LI (E1, E2, SCL, SDA) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input low voltage V IL (SCL, SDA, WC) Input high voltage ...
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... Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction). 28/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR Test conditions (in addition to those in tables 10 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 17. 400 kHz AC characteristics Symbol Alt SCL t t CHCL HIGH t t CLCH LOW ( QL1QL2 t t XH1XH2 XL1XL2 DXCX SU:DAT t t CLDX HD:DAT t t CLQX DH ( CLQV t t CHDL SU:STA t t DLCL HD:STA t t CHDH SU:STO t t DHDL BUF ...
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... SCL) required by the SDA bus line to reach either 0.3V CLQV 0.7V , assuming that R CC 30/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR (1) Test conditions specified in tables 8, 9, Parameter Clock frequency Clock pulse width high Clock pulse width low ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 13. AC waveforms Doc ID 6757 Rev 22 DC and AC parameters 31/43 ...
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... Drawing is not to scale. Table 19. SO8W – 8-lead plastic small outline, 208 mils body width, package data Symbol (number of pins) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 32/43 M24256-BF, M24256-BR, M24256-BW, M24256- millimeters Typ Min Max 2.5 0 0.25 1. ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 20. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Drawing is not to scale. Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to 4 decimal digits. 34/43 M24256-BF, M24256-BR, M24256-BW, M24256- millimeters Typ Min Max 1.200 0.050 0.150 1.000 0.800 1.050 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead mm, outline 1. Drawing is not to scale. 2. The central pad (the area the above illustration) is pulled, internally allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process ...
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... E 1.785 e 0.5 e1 0.866 e2 0.25 e3 0.433 F 0.552 G 0.392 ( Preliminary data. 2. Values in inches are converted from mm and rounded to 4 decimal digits the total number of terminals. 36/43 M24256-BF, M24256-BR, M24256-BW, M24256- Millimeters Typ Min Max 0.55 0.65 0.22 0.27 0.330 0.380 Ø 0.311 1.95 1 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 8 Part numbering Table 24. Ordering information scheme Example: Device type 2 M24 = I C serial access EEPROM Device function 256– = 256 Kbit (32 Kb × 8) Device family B: Without Identification page D: With additional Identification page Operating voltage 2 1.8 to 5.5 V ...
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... Part numbering Table 25. Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) Package SO8N (MN) SO8W (MW) TSSOP (DW) WLCSP (CS) UFDFPN8 (MB) Table 26. Available M24256-DR products (package, voltage range, temperature grade) SO8N (MN) TSSOP (DW) 38/43 M24256-BF, M24256-BR, M24256-BW, M24256-DR M24256-BW 2 5.5 V Range 6, Range 3 Range 6 Range 6 ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR 9 Revision history Table 27. Document revision history Date Revision 29-Jan-2001 10-Apr-2001 16-Jul-2001 02-Oct-2001 13-Dec-2001 12-Jun-2001 22-Oct-2003 02-Sep-2004 22-Feb-2005 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated 1.1 LGA8 and SO8(wide) packages added ...
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... R) Note 1 removed from Table 13: DC characteristics (voltage range SO8W package specifications modified in data. Table 25: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) M24512-x products (package, voltage range, temperature grade) Section 2.5: VSS ground added. Small text changes. ...
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... Figure 6: I2C Fast mode Plus ( MHz): maximum Rbus value versus 10 bus parasitic capacitance (Cbus) on page 10 Caution removed in Section 3.11: ECC (error correction code) and write cycling. M24512-W and M24256-BW offered in the device grade 3 option (automotive temperature range): – Table 8: Operating conditions (voltage range – Table 13: DC characteristics (voltage range – ...
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... XH1XH2 XL1XL2 – Notes modified Figure 13: AC waveforms Section 3.9: Write Identification Page (M24256-D only) 18 corrected.Section 3.17: Reading the Identification Page (M24256-D only) clarified. UFDFPN8 package is now offered (see data, Table 24: Ordering information scheme 19 M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) ...
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... M24256-BF, M24256-BR, M24256-BW, M24256-DR Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...