M95512-WMN6TP STMicroelectronics, M95512-WMN6TP Datasheet - Page 21
![IC EEPROM 512KBIT 5MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M95512-WMN6TP
Manufacturer Part Number
M95512-WMN6TP
Description
IC EEPROM 512KBIT 5MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M95512-RDW6TP.pdf
(48 pages)
Specifications of M95512-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
5MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Organization
64 K x 8
Interface Type
SPI
Maximum Clock Frequency
5 MHz
Access Time
60 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8697-2
M95512-WMN6TP
M95512-WMN6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M95512-WMN6TP
Manufacturer:
ST
Quantity:
7 600
Company:
Part Number:
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Manufacturer:
STMicroelectronics
Quantity:
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Part Number:
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Manufacturer:
ST
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Part Number:
M95512-WMN6TPS
Manufacturer:
ST
Quantity:
20 000
M95512-DR, M95512-W, M95512-R
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction
must have been executed.
The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low,
sending the instruction code and the data byte on Serial Data input (D) and driving Chip
Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write
cycle whose duration is t
shown in
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
also reset when the Write cycle t
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 and SRWD bits:
●
●
The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR
instruction (after t
The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5,
b4, b1, b0. They are always read as 0.
Figure 11. Write Status Register (WRSR) sequence
The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only,
as defined in
The SRWD bit (Status Register Write Disable bit), depending on the signal applied on
the Write Protect pin (W), allows the user to set or reset the write protection mode of
the Status Register. When the Status Register is in the Write-protected mode, the Write
Status Register (WRSR) instruction is not executed.
Figure
S
C
D
Q
W
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
11.
W
Table
).
0
6.
W
1
High Impedance
(specified in
2
Instruction
Doc ID 11124 Rev 14
3
W
4
is complete.
5
Table 17
6
7
MSB
7
8
6
and
9 10 11 12 13 14 15
5
Register In
Table
4
Status
3
19). The instruction sequence is
2
1
0
AI02282D
Instructions
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