M95512-WMN6TP STMicroelectronics, M95512-WMN6TP Datasheet - Page 6
![IC EEPROM 512KBIT 5MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M95512-WMN6TP
Manufacturer Part Number
M95512-WMN6TP
Description
IC EEPROM 512KBIT 5MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M95512-RDW6TP.pdf
(48 pages)
Specifications of M95512-WMN6TP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
512K (64K x 8)
Speed
5MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Organization
64 K x 8
Interface Type
SPI
Maximum Clock Frequency
5 MHz
Access Time
60 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
2 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8697-2
M95512-WMN6TP
M95512-WMN6TP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M95512-WMN6TP
Manufacturer:
ST
Quantity:
7 600
Company:
Part Number:
M95512-WMN6TP
Manufacturer:
STMicroelectronics
Quantity:
28 855
Part Number:
M95512-WMN6TP
Manufacturer:
ST
Quantity:
20 000
Part Number:
M95512-WMN6TPS
Manufacturer:
ST
Quantity:
20 000
Description
1
6/48
Description
The M95512-W, M95512-R and M95512-DR are electrically erasable programmable
memory (EEPROM) devices accessed by a high-speed SPI-compatible bus. In the rest of
the document these devices are referred to as M95512, unless otherwise specified.
The M95512-DR also offers an additional page, named the Identification Page (128 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
Figure 1.
The memory array is organized as 65536 × 8 bit. The device is accessed by a simple serial
interface that is SPI-compatible. The bus signals are C, D and Q, as shown in
Figure
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
1.
Logic diagram
Doc ID 11124 Rev 14
M95512-DR, M95512-W, M95512-R
Table 1
and