M95M01-RMN6TP STMicroelectronics, M95M01-RMN6TP Datasheet
M95M01-RMN6TP
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M95M01-RMN6TP
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M95M01-RMN6TP Summary of contents
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... More than 1 000 000 Write cycles ■ More than 40-year data retention ■ Packages – ECOPACK® (RoHS compliant) July 2009 1 Mbit serial SPI bus EEPROM with high speed clock Doc ID 13264 Rev 7 M95M01-R M95M01-W SO8N (MN) 150 mils width SO8W (MW) 208 mils width WLCSP (CS) 1/41 www.st.com 1 ...
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... Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 13264 Rev 7 M95M01-R, M95M01-W ...
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... M95M01-R, M95M01-W 6.3.2 6.3.3 6.3.4 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 26 8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 8. Operating conditions (M95M01-R6 Table 9. Operating conditions (M95M01-W3 Table 10. AC measurement conditions Table 11. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. DC characteristics (M95M01-R6 Table 13. DC characteristics (M95M01-W3 Table 14. AC characteristics (M95M01-R6 and M95M01-W3, V Table 15 ...
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... M95M01-R, M95M01-W List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. WLCSP connections (bottom view, bump side Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9 ...
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... Description 1 Description The M95M01-R and M95M01-W are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high speed SPI-compatible bus. The memory array is organized as 131 072 × 8 bit. It can also be seen as 512 pages of 256 bytes each. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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... M95M01-R, M95M01-W Figure 2. SO connections 1. See Section 11: Package mechanical data Figure 3. WLCSP connections (bottom view, bump side) M95xxx HOLD for package dimensions, and how to identify pin-1. V SCL CC HOLD Q S Doc ID 13264 Rev 7 Description AI01790D ai16066 7/41 ...
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... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/41 must be held stable and within the specified valid range: CC Table 12). These signals are described next. Doc ID 13264 Rev 7 M95M01-R, M95M01 ...
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... M95M01-R, M95M01-W 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions. ...
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... R SDO SDI SCK SPI Memory R R Device S W HOLD Figure 4) ensures that no device is selected if the bus requirement is met. The typical value 100 k. SHCH Doc ID 13264 Rev 7 M95M01-R, M95M01 SPI Memory SPI Memory R Device Device HOLD ...
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... M95M01-R, M95M01-W 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C) ...
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... CC CC Table 8. (min), V (max)] range defined rises continuously from V CC and the rise time must not vary faster than 1 V/µs. Doc ID 13264 Rev 7 M95M01-R, M95M01-W CC Table 8.). This voltage ). In order to secure a W line with a suitable CC /V package pins reaches a valid and stable V ...
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... M95M01-R, M95M01-W 4.1.4 Power-down During power-down (continuous decrease in the V V operating voltage defined in CC ● deselected (Chip Select S should be allowed to follow the voltage applied on V ● in Standby Power mode (there should not be any internal write cycle in progress). 4.2 Active Power and Standby Power modes When Chip Select (S) is low, the device is selected, and in the Active Power mode ...
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... Table 2. Write-protected block size Status Register bits BP1 14/41 Section 6.3: Read Status Register (RDSR) Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Doc ID 13264 Rev 7 M95M01-R, M95M01-W for a Array addresses protected none 1 8000h - 1 FFFFh 1 0000h - 1 FFFFh 0 0000h - 1 FFFFh ...
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... M95M01-R, M95M01-W 5 Memory organization The memory is organized as shown in Figure 7. Block diagram HOLD Figure 7. High Voltage Control Logic I/O Shift Register Address Register and Counter Doc ID 13264 Rev 7 Memory organization Generator Data Register Status Register 1 Page X Decoder Size of the Read only EEPROM ...
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... Write to Memory Array 8, to send this instruction to the device, Chip Select (S) is driven low Instruction High Impedance Doc ID 13264 Rev 7 M95M01-R, M95M01-W Table 3. Table 3), the device automatically Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 ...
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... M95M01-R, M95M01-W 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high ...
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... Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4. Status Register format b7 SRWD Status Register Write Protect 18/41 Table 4) becomes protected against Write Doc ID 13264 Rev 7 M95M01-R, M95M01-W Figure 10. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit b0 WIP ...
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... M95M01-R, M95M01-W Figure 10. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Doc ID 13264 Rev 7 Instructions Status Register Out MSB 7 AI02031E 19/41 ...
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... Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. Figure 11. Write Status Register (WRSR) sequence 20/41 Figure 11 Instruction Register High Impedance MSB Doc ID 13264 Rev 7 M95M01-R, M95M01 initiated. W Status AI02282D ...
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... M95M01-R, M95M01-W Table 5. Protection modes W SRWD Signal Bit 1 0 Software 0 0 Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The Write Status Register (WRSR) instruction allows the user to change the values of the ...
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... Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. 22/41 Doc ID 13264 Rev 7 M95M01-R, M95M01-W ...
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... Bits A23 to A17 are Don’t Care. 12, to send this instruction to the device, Chip Select (S) is first driven Instruction 24-bit address MSB 6, the most significant address bits are Don’t Care. (1) M95M01-R and M95M01-W A16-A0 Doc ID 13264 Rev Data Out MSB Instructions ...
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... internally executed as a sequence of two consecutive Instruction 24-bit address High Impedance 6, the most significant address bits are Don’t Care. Doc ID 13264 Rev 7 M95M01-R, M95M01-W (as specified in Table 15), at the end of Figure 14, the next byte of (as specified in Table Data byte ...
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... M95M01-R, M95M01-W Figure 14. Page Write (WRITE) sequence shown in Table Instruction 24-bit address Data byte 2 Data byte the most significant address bits are Don’t Care. Doc ID 13264 Rev Data byte Data byte Instructions AI13880 25/41 ...
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... ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95M01-R and M95M01-W devices are qualified at 1 million (1 000 000) write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets. 8 Power-up and delivery state 8 ...
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... M95M01-R, M95M01-W 9 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating conditions (M95M01-R6) Symbol V Supply voltage CC ...
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... M95M01-R, M95M01-W Table 12. DC characteristics (M95M01-R6) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CC (1) I Supply current (Write) CC0 Supply current (Standby I CC1 Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... DC and AC parameters Table 13. DC characteristics (M95M01-W3) Symbol Parameter I Input leakage current LI I Output leakage current LO I Supply current (Read) CC (2) I Supply current (Write) CC0 Supply current I CC1 (Standby Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage ...
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... HHQV LZ ( HLQZ Data concerning the M95M01-W3 are preliminary must never be less than the shortest possible clock period Value guaranteed by characterization, not 100% tested in production. M95M01-R6 and M95M01-W3 Test conditions specified in Parameter Clock frequency S active setup time S not active setup time ...
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... Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time (clock low time): if the SPI bus master offers a read setup time all other cases, t CLQV Doc ID 13264 Rev 7 M95M01-R, M95M01-W ) Table 10 Min. Max. D.C. 2 150 150 200 ...
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... M95M01-R, M95M01-W Figure 16. Serial input timing S tCHSL C tDVCH D Q Figure 17. Hold timing HOLD tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 13264 Rev 7 DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d 33/41 ...
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... DC and AC parameters Figure 18. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN 34/41 tCH tCHCL tCL tQLQH tQHQL Doc ID 13264 Rev 7 M95M01-R, M95M01-W tSHSL tSHQZ AI01449f ...
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... M95M01-R, M95M01-W 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 19. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline 1 ...
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... Doc ID 13264 Rev 7 M95M01-R, M95M01 (1) inches Typ Min 0.0000 0.0594 0.0157 0.0138 0.0079 0.0039 0.1976 0.3000 0.0500 - 0° 0.0197 8 6L_ME Max ...
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... M95M01-R, M95M01-W Figure 21. WLCSP – 8 bump wafer length chip scale package Bump 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 3. Bump position designation as per JESD 95-1, SPP-010. Table 18. WLCSP – 8 bump wafer length chip scale package ...
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... The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 38/41 M95M01 (1) ® (RoHS compliant) Doc ID 13264 Rev 7 M95M01-R, M95M01-W – ...
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... M95M01-R, M95M01-W Table 20. Available products (package, voltage range, temperature grade) Package SO8 (MN) SO8wide (MW) WLCSP (CS) M95M01-R (1 5.5 V) Range 6 Range 6 Range 6 Doc ID 13264 Rev 7 Part numbering M95M01-W (2 5.5 V) Range 39/41 ...
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... ECOPACK text updated under M95M01-W device grade 3 devices added (see Table 9: Operating conditions 7 Table 13: DC characteristics Table 14: AC characteristics (M95M01-R6 and M95M01-W3, VCC ³ 2.5 V) and Table 19: Ordering information Doc ID 13264 Rev 7 M95M01-R, M95M01-W Changes Table 15: AC characteristics (M95M01-R6, 1). ...
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... M95M01-R, M95M01-W Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...