M95M01-DFDW6TP STMicroelectronics, M95M01-DFDW6TP Datasheet
M95M01-DFDW6TP
Specifications of M95M01-DFDW6TP
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M95M01-DFDW6TP Summary of contents
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... Additional Write lockable page (Identification page) Write Protect: quarter, half or whole memory array High-speed clock: 16 MHz Single supply voltage: – 1 5.5 V for M95M01-R – 1 5.5 V for M95M01-DF Operating temperature range: from -40° +85°C Enhanced ESD protection More than 4 million Write cycles ...
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... Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 13264 Rev 11 M95M01-DF M95M01-R ...
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... Write to Memory Array (WRITE 6.6.1 6.7 Read Identification Page (available only in M95M01-D devices 6.8 Write Identification Page (available only in M95M01-D devices 6.9 Read Lock Status (available only in M95M01-Ddevices 6.10 Lock ID (available only in M95M01-D devices Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9. Operating conditions (M95M01-R, device grade Table 10. Operating conditions (M95M01-DF, device grade Table 11. AC measurement conditions Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14 ...
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... Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 38 Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 25. M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 40 Doc ID 13264 Rev 11 List of figures 5/45 ...
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... The M95M01 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 131072 x 8 bits, accessed through the SPI bus. The M95M01-R devices can operate with a supply range from 1 5.5 V, the M95M01-DF devices can operate with a supply range from 1 5.5 V. These devices are guaranteed over the -40 ° ...
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... See Section 10: Package mechanical data Figure 3. WLCSP connections for M95M01-DFCS6TP/K (top view, marking side, with balls on the underside) Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet (UV) light, EEPROM dice delivered in wafer form or in WLCSP package by STMicroelectronics must never be exposed to UV light ...
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... The memory is organized as shown in the following figure. Figure 4. Block diagram HOLD 8/45 High voltage Control logic generator I/O shift register Data Address register register and counter Identification page X decoder Doc ID 13264 Rev 11 M95M01-DF M95M01-R Status register 1/4 Size of the Read only EEPROM 1/2 area 1 page MS19733V1 ...
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... M95M01-DF M95M01-R 3 Signal description During all operations (min (max All of the input and output signals must be held high or low (according to voltages specified described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C) ...
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... Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 V supply voltage the supply voltage. CC 3.8 V ground the reference for all signals, including the V SS 10/45 supply voltage. CC Doc ID 13264 Rev 11 M95M01-DF M95M01-R ...
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... M95M01-DF M95M01-R 4 Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data ...
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... Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 6. SPI modes supported CPOL CPHA 12/45 MSB Doc ID 13264 Rev 11 M95M01-DF M95M01-R Figure 6, is the clock polarity when the MSB AI01438B ...
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... M95M01-DF M95M01-R 5 Operating features 5.1 Supply voltage (V 5.1.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V in Section 9: DC and AC end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (t ...
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... In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command. 14/ (a)(b) Hold condition Figure 7). Doc ID 13264 Rev 11 M95M01-DF M95M01-R supply voltage below the minimum CC Section 9: DC and AC Section 9: DC and AC parameters). Hold condition ), CC ai02029E ...
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... M95M01-DF M95M01-R The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions ...
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... Each instruction starts with a single-byte code, as summarized invalid instruction is sent (one not contained in deselects itself. Table 3. Instruction set Instruction WREN WRDI RDSR WRSR READ WRITE Table 4. M95M01-D instruction set Instruction WREN WRDI RDSR WRSR READ WRITE Read Identification Page Write Identification Page Read Lock Status Lock ID 1 ...
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... M95M01-DF M95M01-R 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state ...
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... The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Figure 9. Write Disable (WRDI) sequence 18/ send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q Doc ID 13264 Rev 11 M95M01-DF M95M01 AI03750D ...
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... M95M01-DF M95M01-R 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Q 20/ Figure 11 Instruction 7 High Impedance MSB Doc ID 13264 Rev 11 M95M01-DF M95M01-R BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Status Register AI02282D b0 WIP ...
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... M95M01-DF M95M01-R Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self- timed Write cycle that takes t and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle t , and 0 when the Write cycle is complete ...
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... Chip Select (S) is first driven 24-bit address MSB Doc ID 13264 Rev 11 M95M01-DF M95M01 Data Out 1 Data Out MSB AI13878 ...
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... M95M01-DF M95M01-R When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle ...
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... Instruction 24-bit address Data byte 2 Data byte Doc ID 13264 Rev 11 M95M01-DF M95M01 Data byte Data byte MS30906V1 ...
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... M95M01-DF M95M01-R 6.6.1 Cycling with Error Correction Code (ECC) The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value ...
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... Instructions 6.7 Read Identification Page (available only in M95M01-D devices) The Identification Page (256 bytes additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D) ...
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... M95M01-DF M95M01-R 6.8 Write Identification Page (available only in M95M01-D devices) The Identification Page (256 bytes additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D) ...
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... Instructions 6.9 Read Lock Status (available only in M95M01-Ddevices) The Read Lock Status instruction (see Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data Output (Q “ ...
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... M95M01-DF M95M01-R 6.10 Lock ID (available only in M95M01-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high ...
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... Initial delivery state The device is delivered with the memory array set to all 1s (each byte = FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 30/45 Doc ID 13264 Rev 11 M95M01-DF M95M01-R ...
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... M95M01-DF M95M01-R 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... DC and AC parameters 9 DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 9. Operating conditions (M95M01-R, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 10. Operating conditions (M95M01-DF, device grade 6) Symbol V Supply voltage CC T Ambient operating temperature A Table 11 ...
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... M95M01-DF M95M01-R Table 12. Capacitance Symbol C Output capacitance (Q) OUT Input capacitance ( Input capacitance (other pins) 1. Sampled only, not 100% tested Table 13. Cycling performance by groups of four bytes Symbol Parameter Ncycle Write cycle endurance 1. Cycling performance for products identified by process letters KB. ...
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... Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage 1.7 V for the M95M01-DF For devices identified by process letter K. 3. Characterized value, not tested in production. 34/45 Test conditions ...
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... M95M01-DF M95M01-R Table 16. AC characteristics Test conditions specified in Symbol Alt. Parameter f f Clock frequency C SCK active setup time SLCH CSS1 not active setup time SHCH CSS2 Deselect time SHSL active hold time CHSH CSH t S not active hold time ...
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... DC and AC parameters Figure 20. Serial input timing S tCHSL C tDVCH D Q Figure 21. Hold timing HOLD 36/45 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 13264 Rev 11 M95M01-DF M95M01-R tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...
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... M95M01-DF M95M01-R Figure 22. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 13264 Rev 11 DC and AC parameters tSHSL tSHQZ AI01449f 37/45 ...
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... Doc ID 13264 Rev 11 M95M01-DF M95M01 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.0110 0.0067 0.1929 0.1890 0.2362 0.2283 ...
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... M95M01-DF M95M01-R Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data Symbol Values in inches are converted from mm and rounded to four decimal digits. ...
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... Package mechanical data Figure 25. M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline Reference (4X) Wafer back side Bump eee Z Ø Ø 1. Drawing is not to scale. 40/45 bbb Z Detail A aaa A A2 Side view A1 b ccc ddd M Z Detail A Rotated 90 ° Doc ID 13264 Rev 11 ...
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... M95M01-DF M95M01-R Table 19. M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data Symbol (number of terminals) aaa bbb ccc ddd eee 1. Values in inches are converted from mm and rounded to four decimal digits. millimeters Typ Min Max 0.540 ...
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... P = RoHS compliant and halogen-free (ECOPACK®) (1) Process /K= Manufacturing technology code 1. The process letters apply to WLCSP devices only. The process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. 42/45 M95M01 Doc ID 13264 Rev 11 M95M01-DF M95M01 ...
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... ECOPACK text updated under M95M01-W device grade 3 devices added (see Table 9: Operating conditions 7 Table 13: DC characteristics Table 14: AC characteristics (M95M01-R6 and M95M01-W3, V and Table 20: Ordering information Added TSSOP package. Updated – Table 12: DC characteristics (M95M01-R6) – Table 13: DC characteristics (M95M01-W3) – ...
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... Datasheet split into: – M95M01-125 datasheet for automotive products (range 3), – M95M01-DF, M95M01-R (this datasheet) for standard products (range 6). Updated: – WLCSP package dimensions: WLCSP 8-bump wafer-level chip scale package outline M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package ...
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... M95M01-DF M95M01-R Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...