M95M01-RMN6G STMICROELECTRONICS [STMicroelectronics], M95M01-RMN6G Datasheet
M95M01-RMN6G
Related parts for M95M01-RMN6G
M95M01-RMN6G Summary of contents
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... July 2007 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1 Mbit serial SPI bus EEPROM with high speed clock SO8N (MN) 150 mils width SO8W (MW) 208 mils width Rev 4 M95M01-R Preliminary Data 1/39 www.st.com 1 ...
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... Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 2/ Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 M95M01-R ...
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... M95M01-R 6.3.2 6.3.3 6.3.4 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 27 8 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 Part numbering ...
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... Table 15. SO8W – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 16. Ordering information scheme Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4/39 2.5 V and –40° ° < 2.5 V and –40° ° ( M95M01-R ...
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... M95M01-R List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9 ...
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... Description 1 Description The M95M01 electrically erasable programmable memory (EEPROM) device accessed by a high speed SPI-compatible bus. The memory array is organized as 131 072 × 8 bit. It can also be seen as 512 pages of 256 bytes each. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken Low ...
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... M95M01-R Figure 2. SO and TSSOP connections 1. See Section 11: Package mechanical M95xxx HOLD AI01790D for package dimensions, and how to identify pin-1. Description 7/39 ...
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... During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 8/39 must be held stable and within the specified valid range: CC Table 11). These signals are described next. M95M01 ...
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... M95M01-R 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write instructions. ...
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... R SDO SDI SCK SPI Memory R R Device S W HOLD Figure 3) ensures that no device is selected if the Bus requirement is met. SHCH M95M01 SPI Memory SPI Memory R Device Device HOLD ...
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... M95M01-R 3.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). ...
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... V CC has reached the power on reset threshold voltage (this threshold is CC operating voltage defined Table 8.). In order to line with During this SS CC voltage via a suitable pull-up resistor. CC Table 8). M95M01-R voltage package ), a CC ...
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... M95M01-R 4.1.4 Power-down At Power-down (continuous decrease in V operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (S) should be allowed to follow the voltage applied on V internal Write cycle in progress). ...
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... Read Status Register (RDSR) and Read (READ) instructions). The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus. 14/39 Hold Condition Section 6.3: Read Status Register (RDSR) M95M01-R Hold Condition AI02029D for a ...
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... M95M01-R Table 2. Write-protected block size Status Register bits BP1 Protected block BP0 0 none 1 Upper quarter 0 Upper half 1 Whole memory Operating features Array addresses protected none 1 8000h - 1 FFFFh 1 0000h - 1 FFFFh 0 0000h - 1 FFFFh 15/39 ...
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... Memory organization 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD 16/39 Figure 6. High Voltage Control Logic I/O Shift Register Address Register and Counter Generator Data Register Status Register 1 Page X Decoder M95M01-R Size of the Read only EEPROM area AI01272C ...
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... M95M01-R 6 Instructions Each instruction starts with a single-byte code, as summarized invalid instruction is sent (one not contained in deselects itself. Table 3. Instruction set Instruction WREN Write Enable WRDI Write Disable RDSR Read Status Register WRSR Write Status Register READ Read from Memory Array ...
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... The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Figure 8. Write Disable (WRDI) sequence 18/ send this instruction to the device, Chip Select (S) is driven Low Instruction High Impedance M95M01-R 7 AI03750D ...
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... M95M01-R 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Instructions Figure 9. Read Status Register (RDSR) sequence High Impedance Q 20/ Instruction Status Register Out MSB Status Register Out MSB M95M01-R 7 AI02031E ...
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... M95M01-R 6.4 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... The values in the BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the BP1 and (HPM) BP0 bits cannot be changed Table 4. M95M01-R Memory content (1) Protected area Unprotected area Ready to accept Write Protected Write instructions Ready to accept Write Protected ...
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... M95M01-R Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. ...
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... Chip Select (S) is first driven Instruction 24-bit address MSB 6, the most significant address bits are Don’t Care. (1) M95M01-R A16- Data Out MSB M95M01-R Data Out 2 7 AI13878 ...
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... M95M01-R 6.6 Write to Memory Array (WRITE) As shown in Figure Low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input data. In the case of latched in, indicating that the instruction is being used to write a single byte ...
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... Data byte the most significant address bits are Don’t Care Data byte Data byte M95M01 AI13880 ...
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... ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word therefore recommended to write by words of 4 bytes in order to benefit from the larger amount of Write cycles. The M95M01-R device is qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets. 8 Power-up and delivery state 8 ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 , R2=500 ) 28/39 Table 7 Parameter (2) M95M01-R may cause permanent damage to Min. Max. Unit –40 130 °C – ...
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... M95M01 and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... –0 –0 – M95M01-R Min Max Unit ± 2 µA ± 2 µA 1 µA 5 µA –0.45 0. –0.45 0 ...
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... M95M01-R Table 12. AC characteristics ( Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ...
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... Clock low setup time before HOLD active Clock low setup time before HOLD not active Output Disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output High-Z Write time M95M01 °C A Table 9 Min. Max. Unit D.C. 2 ...
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... M95M01-R Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD tSLCH tCHDX tCLCH MSB IN High Impedance tHLCH tCLHL tHLQZ DC and AC parameters tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B 33/39 ...
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... DC and AC parameters Figure 17. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D 34/39 tCH tCLQV tQLQH tQHQL M95M01-R tCL tSHQZ LSB OUT AI01449e ...
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... M95M01-R 11 Package mechanical Figure 18. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc ...
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... millimeters Typ Min Max 2.50 0.00 0.25 1.51 2.00 0.40 0.35 0.51 0.20 0.10 0.35 0.10 6.05 5.02 6.22 7.62 8.89 1.27 – – 0.50 0. 6L_ME inches Typ Min 0.000 0.059 0.016 0.014 0.008 0.004 0.198 0.300 0.050 – 0 0.020 8 M95M01-R Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 – 10 0.031 ...
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... T = tape and reel packing Plating technology ECOPACK® (RoHS compliant) 1. Ordering information related to the M95M01-R identified with the process letter "A". For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. ...
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... The device endurance is specified at more than 1 000 000 (1 million) 3 cycles (corrected on page Schmitt trigger inputs for enhanced noise margin on page and V values modified according to voltage range characteristics. Changes Table 13: AC characteristics (VCC < 2.5 V °C). Small text changes. 1). added to M95M01-R Features Table 11: ...
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... M95M01-R Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...