M95M01-RMN6G STMICROELECTRONICS [STMicroelectronics], M95M01-RMN6G Datasheet - Page 17
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M95M01-RMN6G
Manufacturer Part Number
M95M01-RMN6G
Description
1 Mbit serial SPI bus EEPROM with high speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M95M01-RMN6G.pdf
(39 pages)
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M95M01-R
6
6.1
Instructions
Each instruction starts with a single-byte code, as summarized in
If an invalid instruction is sent (one not contained in
deselects itself.
Table 3.
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
High.
Figure 7.
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction
Figure
Instruction set
Write Enable (WREN) sequence
S
C
D
Q
Write Enable
Write Disable
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
7, to send this instruction to the device, Chip Select (S) is driven Low,
High Impedance
0
1
Description
2
Instruction
3
4
5
6
Table
7
3), the device automatically
AI02281E
Table
Instruction format
3.
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Instructions
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