M25P32-VME6G NUMONYX, M25P32-VME6G Datasheet - Page 27

• Manufacturer Part Number: M25P32-VME6G
• Description: IC FLASH 32MBIT 75MHZ 8VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P32-VME6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFPN
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VDFPN
• No. Of Pins: 8
• Base Number: 25
• Frequency: 75MHz
• Ic Generic: RoHS Compliant
• Memory Configuration: 4M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M25P32
Table 7.
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/V
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W/V
●
●
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
●
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W/V
If Write Protect (W/V
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
W/V
signal
Table
1
0
1
0
PP
If Write Protect (W/V
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/V
even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/V
or by driving Write Protect (W/V
(SRWD) bit.
2.
SRWD
PP
bit
0
0
1
1
) Low
Protection modes
PP
) High.
Protected
Hardware
Protected
Software
(SPM)
(HPM)
Mode
PP
) is permanently tied High, the Hardware Protected Mode (HPM) can
PP
PP
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Write Protection of the
) is driven High, it is possible to write to the Status Register
) is driven Low, it is not possible to write to the Status Register
Status Register
PP
) is driven High or Low.
PP
) Low after setting the Status Register Write Disable
Protected against
Page Program,
Sector Erase and
Bulk Erase
Protected against
Page Program,
Sector Erase and
Bulk Erase
Protected area
Table
7.
Memory content
(1)
Unprotected area
Ready to accept
Page Program and
Sector Erase
instructions
Ready to accept
Page Program and
Sector Erase
instructions
PP
):
Instructions
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(1)