C8051T320-GQR Silicon Labs, C8051T320-GQR Datasheet - Page 9
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C8051T320-GQR
Manufacturer Part Number
C8051T320-GQR
Description
8-bit Microcontrollers - MCU USB-OTP-16K-ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051T322-GQR.pdf
(292 pages)
Specifications of C8051T320-GQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
C8051T320-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 138
Figure 22.4. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 139
Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 140
Figure 23.1. USB0 Block Diagram ......................................................................... 155
Figure 23.2. USB0 Register Access Scheme ........................................................ 158
Figure 23.3. USB FIFO Allocation ......................................................................... 164
Figure 24.1. SMBus Block Diagram ...................................................................... 188
Figure 24.2. Typical SMBus Configuration ............................................................ 189
Figure 24.3. SMBus Transaction ........................................................................... 190
Figure 24.4. Typical SMBus SCL Generation ........................................................ 192
Figure 24.5. Typical Master Write Sequence ........................................................ 201
Figure 24.6. Typical Master Read Sequence ........................................................ 202
Figure 24.7. Typical Slave Write Sequence .......................................................... 203
Figure 24.8. Typical Slave Read Sequence .......................................................... 204
Figure 25.1. UART0 Block Diagram ...................................................................... 209
Figure 25.2. UART0 Baud Rate Logic ................................................................... 210
Figure 25.3. UART Interconnect Diagram ............................................................. 211
Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 211
Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 212
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 213
Figure 26.1. UART1 Block Diagram ...................................................................... 217
Figure 26.2. UART1 Timing Without Parity or Extra Bit ......................................... 219
Figure 26.3. UART1 Timing With Parity ................................................................ 219
Figure 26.4. UART1 Timing With Extra Bit ............................................................ 219
Figure 26.5. Typical UART Interconnect Diagram ................................................. 220
Figure 26.6. UART Multi-Processor Mode Interconnect Diagram ......................... 221
Figure 27.1. SPI Block Diagram ............................................................................ 227
Figure 27.2. Multiple-Master Mode Connection Diagram ...................................... 229
Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Figure 27.5. Master Mode Data/Clock Timing ....................................................... 232
Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 232
Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 233
Figure 27.8. SPI Master Timing (CKPHA = 0) ....................................................... 237
Figure 27.9. SPI Master Timing (CKPHA = 1) ....................................................... 237
Figure 27.10. SPI Slave Timing (CKPHA = 0) ....................................................... 238
Figure 27.11. SPI Slave Timing (CKPHA = 1) ....................................................... 238
Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 243
Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 244
Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 245
Figure 28.4. Timer 2 16-Bit Mode Block Diagram ................................................. 250
Figure 28.5. Timer 2 8-Bit Mode Block Diagram ................................................... 251
Connection Diagram .......................................................................... 229
Connection Diagram .......................................................................... 230
C8051T620/621/320/321/322/323
Rev. 1.1
9
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