CY7C109D-10VXI Cypress Semiconductor Corp, CY7C109D-10VXI Datasheet - Page 5

• Manufacturer Part Number: CY7C109D-10VXI
• Description: IC SRAM 1MBIT 10NS 32SOJ
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C109D-10VXI

• Memory Size: 1M (128K x 8)
• Package / Case: 32-SOJ
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 10 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 80 mA
• Organization: 128 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Density: 1Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Supply Current: 80mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2010-5

Switching Characteristics
Notes
Document #: 38-05468 Rev. *F
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
7. t
8. t
9. At any given temperature and voltage condition, t
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
Parameter
I
a high impedance state.
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
[10]
[10]
OL
POWER
HZOE
/I
[7]
OH
, t
HZCE
and 30-pF load capacitance.
gives the minimum amount of time that the power supply should be at typical V
and t
[11, 12]
HZWE
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
Write Cycle Time
CE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
CC
1
1
1
1
1
1
are specified with a load capacitance of 5 pF as in part (c) of
(typical) to the first access
LOW to Data Valid, CE
LOW to Low Z, CE
HIGH to High Z, CE
LOW to Power-Up, CE
HIGH to Power-Down, CE
LOW to Write End, CE
(Over the Operating Range)
[9]
[8, 9]
[8, 9]
2
2
Description
HIGH to Low Z
HZCE
LOW to High Z
2
2
2
HIGH to Write End
HIGH to Power-Up
HIGH to Data Valid
is less than t
2
LOW to Power-Down
LZCE
1
[9]
, t
LOW, CE
[8, 9]
HZOE
“AC Test Loads and Waveforms
[6]
is less than t
2
HIGH, and WE LOW. CE
CC
LZOE
values until the first memory access can be performed
, and t
HZWE
HZWE
and t
1
is less than t
SD
[5]
and WE must be LOW and CE
Min
100
10
10
” on page
.
3
0
3
0
7
7
0
0
7
6
0
3
7C1009D-10
7C109D-10
LZWE
4. Transition is measured when the outputs enter
for any given device.
Max
10
10
10
5
5
5
5
2
CY7C1009D
HIGH to initiate a write, and
CY7C109D
Page 5 of 12
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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