CY62147EV30LL-45BVXI Cypress Semiconductor Corp, CY62147EV30LL-45BVXI Datasheet - Page 7

• Manufacturer Part Number: CY62147EV30LL-45BVXI
• Description: IC SRAM 4MBIT 45NS 48VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62147EV30LL-45BVXI

• Memory Size: 4M (256K x 16)
• Package / Case: 48-VFBGA
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3 V
• Memory Configuration: 256K X 16
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 18b
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Supply Current: 20mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2072; CY62147EV30LL-45BVXI

Switching Waveforms
Notes
Document Number: 38-05440 Rev. *J
22. The device is continuously selected. OE, CE = V
23. WE is HIGH for read cycle.
24. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE
25. Address valid before or similar to CE and BHE, BLE transition LOW.
DATA OUT
CURRENT
ADDRESS
DATA OUT
ADDRESS
BHE/BLE
SUPPLY
and CE
V
OE
CE
CC
2
such that when CE
PREVIOUS DATA VALID
HIGH IMPEDANCE
1
is LOW and CE
t
PU
t
Figure 6. Read Cycle No. 1: Address Transition Controlled
LZCE
t
LZBE
t
t
ACE
LZOE
2
t
Figure 7. Read Cycle No. 2: OE Controlled
DBE
is HIGH, CE is LOW. For all other cases CE is HIGH.
IL
t
50%
OHA
, BHE, BLE, or both = V
t
DOE
t
AA
t
RC
IL
.
t
RC
DATA VALID
[23, 24, 25]
DATA VALID
[22, 23]
CY62147EV30 MoBL
t
HZBE
t
t
HZOE
HZCE
t
PD
50%
IMPEDANCE
HIGH
Page 7 of 16
I
I
CC
SB
1
®
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