CY7C1338G-100AXC Cypress Semiconductor Corp, CY7C1338G-100AXC Datasheet - Page 13
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CY7C1338G-100AXC
Manufacturer Part Number
CY7C1338G-100AXC
Description
IC SRAM 4MBIT 100MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1338G-100AXC.pdf
(21 pages)
Specifications of CY7C1338G-100AXC
Memory Size
4M (128K x 32)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
100MHz
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
8 ns
Maximum Clock Frequency
100 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
205 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
3.3 V
Density
4Mb
Access Time (max)
8ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Supply Current
205mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
32b
Number Of Words
128K
Memory Configuration
128K X 32
Clock Frequency
100MHz
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1338G-100AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1338G-100AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Timing Diagrams
Write Cycle Timing
Notes
Document Number: 38-05521 Rev. *F
19. On this diagram, when CE is LOW: CE
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data in (D)
ADDRESS
BW
BWE,
ADSP
ADSC
[A:D]
GW
ADV
CE
CLK
OE
BURST READ
High-Z
t ADS
[19, 20]
t CES
t AS
(continued)
A1
t ADH
t CEH
t
t AH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t
Single WRITE
CL
t
DS
D(A1)
1
is LOW, CE
t
t ADH
DH
A2
2
is HIGH and CE
D(A2)
DON’T CARE
3
D(A2 + 1)
t
WES
is LOW. When CE is HIGH: CE
BURST WRITE
t
WEH
D(A2 + 1)
UNDEFINED
[A:D]
ADV suspends burst
LOW.
D(A2 + 2)
ADSC extends burst
1
is HIGH or CE
D(A2 + 3)
t ADS
2
A3
D(A3)
is LOW or CE
t ADH
t ADVS
Extended BURST WRITE
t WES
D(A3 + 1)
t ADVH
t WEH
3
is HIGH.
CY7C1338G
D(A3 + 2)
Page 13 of 21
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