M58LT256JST8ZA6E NUMONYX, M58LT256JST8ZA6E Datasheet - Page 16

• Manufacturer Part Number: M58LT256JST8ZA6E
• Description: IC FLASH 256MBIT 85NS 64TBGA
• Manufacturer: NUMONYX

Specifications of M58LT256JST8ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (16Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bus operations
3
3.1
3.2
3.3
3.4
16/108
Bus operations
There are six standard bus operations that control the device. These are bus read, bus
write, address latch, output disable, standby and reset. See
summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
Bus read
Bus read operations output the contents of the memory array, the electronic signature, the
Status Register and the common Flash interface. Both Chip Enable and Output Enable must
be at V
device. Output Enable should be used to gate data onto the output. The data read depends
on the previous command written to the memory (see
Figures 9,
for details of when the output becomes valid.
Bus write
Bus write operations write commands to the memory or latch input data to be programmed.
A bus write operation is initiated when Chip Enable and Write Enable are at V
Enable at V
Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the
write operation by toggling Latch Enable (when Chip Enable is at V
must be tied to V
See Figures
characteristics for details of the timing requirements.
Address latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at V
Latch Enable.
Output disable
The outputs are high impedance when the Output Enable is at V
IL
during address latch operations. The addresses are latched on the rising edge of
IL
to perform a read operation. The Chip Enable input should be used to enable the
10
IH
15
. Commands, input data and addresses are latched on the rising edge of Write
and
and 16, Write AC waveforms, and Tables
IH
11
during the bus write operation.
Read AC waveforms, and Tables
Section 4: Command
22
24
and
M58LT256JST, M58LT256JSB
Table 3: Bus operations
and 25, Write AC
23
IH
Read AC characteristics
.
IL
). The Latch Enable
interface). See
IL
with Output
for a