M58LT256JST8ZA6E NUMONYX, M58LT256JST8ZA6E Datasheet - Page 21

• Manufacturer Part Number: M58LT256JST8ZA6E
• Description: IC FLASH 256MBIT 85NS 64TBGA
• Manufacturer: NUMONYX

Specifications of M58LT256JST8ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (16Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M58LT256JST, M58LT256JSB
4.5
4.6
Clear Status Register command
The Clear Status Register command resets (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the
Status Register.
One bus write cycle is required to issue the Clear Status Register command. The Clear
Status Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to ’1’
and all previous data in the block is lost.
If the block is protected, then the erase operation aborts, the data in the block is not
changed, and the Status Register outputs the error.
Two bus write cycles are required to issue the command.
●
●
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and
SR5 are set, and the command is aborted.
Once the command is issued, the bank enters read Status Register mode and any read
operation within the addressed bank outputs the contents of the Status Register. A Read
Array command is required to return the bank to read array mode.
During block erase operations the bank containing the block being erased only accepts the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend commands, and all other commands are ignored.
The block erase operation aborts if Reset, RP, goes to V
guaranteed when the Block Erase operation is aborted, the block must be erased again.
Refer to
not being erased.
Typical erase times are given in
See
flowchart for using the Block Erase command.
Appendix
The first bus cycle sets up the Block Erase command.
The second latches the block address and starts the Program/Erase Controller.
Section 8
C,
Figure 23: Block erase flowchart and pseudocode
for detailed information about simultaneous operations allowed in banks
Table 16: Program/erase times and endurance cycles
IL
. As data integrity cannot be
for a suggested
Command interface
21/108
,
.